A detection time gate is a selected interval during which a photodetector's output contributes to a measurement. Its start delay and duration are measured relative to a trigger or another time reference. The gate may control an integrating amplifier, an electronic counter or a software selection of recorded events; it need not physically switch off the light.
A gated integrator supplies a concrete apparatus. Stanford Research Systems' SR250 uses a triggerable gate generator, a fast integrator and a readout normalized by gate width. Its gate monitor can be displayed alongside the signal on an oscilloscope to check their relative timing.[ref] An integrated area and a gate-averaged amplitude are different output quantities: dividing an area by changes its units.
An original photon counting example shows the gate-width tradeoff. Suppose an ideal decaying signal has expected count rate for , and a constant background has rate . A gate from0 to collects expected countsIf signal and background counts are independent Poisson distributions and the background mean is known exactly, the background-corrected count has variance . Its signal-to-noise ratio is . With chosen values and , a gate of width gives about63.2signal counts,100background counts and ratio4.95. A gate of width collects95.0signal counts but300background counts, reducing that ratio to4.78. More collected signal alone does not guarantee a better measurement.
This example assumes ideal event registration; detector dead time, non-Poisson backgrounds or an estimated rather than known background alter the calculation. Gate timing jitter can also vary the admitted part of a rapidly changing signal. Gate placement and duration should therefore be checked against the actual waveform, background and measurement objective, rather than chosen solely from the nominal pulse width.
A gate-normalized detector output reports an integrated detector signal divided by the duration of the detection time gate. For an input electric potential difference waveform and a gate from to , the input-referred average isIts units are those of electric potential difference, whereas the integral has units of electric potential difference times time. The SR250 gated integrator implements integration followed by gate-width normalization and an adjustable amplification stage.[ref]
SR250 Gated Integrator by Stanford Research Systems. PDFp1, Overview and Signal Inputs
For an original idealized detector pulse, take from0 to4nanoseconds and zero outside that interval. A gate covering0–4nanoseconds integrates and reports an average of2millivolts. A gate covering0–8nanoseconds integrates the same area but reports1millivolt. Thus unchanged admitted pulse area need not give an unchanged normalized output.
The gate average also differs from the average over a full repetition period. For the same pulse repeated once per microsecond, the full-period mean is only8microvolts. Comparing instruments therefore requires knowing whether the reported quantity is pulse area, within-gate average or full-period average.
A constant baseline contributesGate-width normalization does not remove that baseline. A separate reference or subtraction measurement is needed to distinguish it from the desired signal.
An apparatus check overlays the gate monitor and detector waveform on an oscilloscope, then varies the gate width while keeping its start fixed. A flat plateau should retain its input-referred average while the gate remains inside it; a short pulse diluted by additional quiet time behaves like the example above. Gate timing jitter and gate-width jitter can alter which signal portion is admitted and which duration is used for normalization.[ref]
SR250 Gated Integrator by Stanford Research Systems. PDFp2, Gate Timing and Additional Outputs
Gate timing jitter is shot-to-shot variation in the timing of a detection time gate relative to the signal being measured. It differs from a fixed delay error: repeated gates may have the correct mean delay while admitting different portions of a rapidly varying detector signal. The SR250 catalogue describes a trigger-controlled gate, finite delay jitter and a gate-monitor output that can be overlaid with the signal on an oscilloscope.[ref]
For an original sensitivity derivation, let a reproducible baseline-corrected electric current waveform be and the intended integrated electric charge beSmall edge errors giveIf both edges shift by the same amount, the gate width is unchanged butThus a gate translating within a flat plateau has little first-order sensitivity, while a gate whose edges intersect different signal levels can be sensitive even at fixed width.
For stipulated edge currents and , a common timing error with standard deviation contributes approximately charge standard deviation. This calculation assumes smooth waveform values near both edges and timing excursions small enough for linearization. A gate crossing an abrupt onset requires the actual waveform integral.
Gate-width jitter is a separate effect. For a constant plateau current , , so even though a common gate translation would cancel. More generally, the edge-error contribution has varianceThe covariance determines whether two individually noisy edges largely preserve the width.
An apparatus check records both the gate monitor and signal waveform over many triggers, using the same time reference, to estimate relative delay and width distributions. A single aligned trace establishes neither distribution. Timing motion shared by the pulse and gate can cancel in their relative delay; the uncertainty relevant to the measured charge is their relative timing, not solely a gate generator's standalone specification.
Gate-width jitter is shot-to-shot variation in the duration of a detection time gate. If its opening and closing times are , then . Both edges can have substantial gate timing jitter while their difference remains stable. A common shift changes delay without changing width.
For small timing fluctuations,With equal edge standard deviations and correlation coefficient , this becomes . The covariance identity is exact whenever those variances exist. It separates width stability from the jitter of either edge measured alone.
For an original example, let both edges have standard deviation . Independent edge errors give ; correlation instead gives . At nominal width , those are relative width fluctuations of about 1.414 percent and 0.1414 percent. Assuming independence would overestimate the second width uncertainty by a factor of ten.
If a flat, baseline-corrected electric current fills the gate, the integrated electric charge is , so . At the nominal charge is , with respective standard deviations and . A varying waveform also introduces sensitivity to where the edges fall; the gate timing jitter article gives the general edge-current formula.
A gate-normalized detector output can report instead of charge. For an exactly constant current and accurately known actual width, that ratio is despite width variation. Dividing by a fixed nominal width instead retains the width-induced variation. The SR250 documentation describes integration followed by gate-width normalization, and provides a gate monitor for checking timing.[ref]
SR250 Gated Integrator by Stanford Research Systems. PDF pp. 1–2, Overview, Gate Timing and Additional Outputs
An apparatus check measures both edges relative to a common reference over repeated triggers and computes their difference for each shot. Measuring the two edge jitter distributions separately without their covariance cannot determine width jitter. Readout time resolution and the threshold used to define an edge are also part of that measurement.
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