Impedance bridging with capacitive input
ID: impedance-bridging-with-capacitive-input
Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.
For source resistance , receiving resistance and input capacitance , use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is , soHere is the open-circuit source phasor; is the loaded terminal phasor. The impedance bridging objective is near one, rather than merely a large quoted DC input resistance.
The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen , the capacitive bridging complex-error bandwidth condition requiresA negative numerator means even the DC loading error exceeds the tolerance.
In an original example, , and give . A one-percent complex-error tolerance permits frequencies only up to about . At the amplitude ratio remains about , but the phase is about and the complex error about . A small amplitude error can coexist with a materially larger waveform-phase error.
High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.
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