 Integrator reset settling time

The integrator reset settling time is the time required to reach a stated error band under the reset/readout sequence. It is not merely the switch's control propagation delay. The primary switch tutorial distinguishes switching time from complete-circuit settling.^[ref]

The integrator reset article derives an ideal residual $V_0{e}^{-T/\tau }$, with $\tau =R_{\mathrm{on}}C$. A focused extension includes an opening pedestal whose magnitude is at most $p$. A conservative final-error bound isTo guarantee $|e|\le \epsilon$ from this bound, require $\epsilon >p$ andwhen the logarithm is positive. This reset error budget with a persistent pedestal assigns separate parts of the tolerance to the residual and the opening event.

For stipulated $|V_0|=0.40\mathrm{V}$, $\tau =20\mu \mathrm{s}$, $p=2\mathrm{mV}$ and $\epsilon =3\mathrm{mV}$, the required duration is about $119.8\mu \mathrm{s}$. A tolerance of $1\mathrm{mV}$ cannot be guaranteed by waiting longer under the same pedestal bound. Accidental cancellation of opposite-sign errors is not a worst-case guarantee.

Measure the output against a stated band at a reproducible delay after opening. Ringing, amplifier drive limits and prior overload can invalidate a single-exponential model; the device datasheet treats output-overload recovery separately.^[ref] The resulting acquisition exclusion is part of integrator reset dead time.