Solution

ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2003/functional-programming-data-structures-and-algorithms-procedural-programming-and-digital-hardware/10/b/iii/solution

Use a three-state Moore machine for a rearmable one-cycle pulse generator. Call the states Ready, Pulse, and Wait. Their outputs are respectively , and initialize in Ready. Labels below are the sampled input pair ab; because simultaneous ones are unspecified, choose reset priority for 11.
Figure 1.
Rearmable one-cycle pulse generator and reproduction of the specified timing behavior
. Details.
The complete chosen state transition table is
State
ReadyReadyReadyPulseReady
PulseWaitReadyWaitReady
WaitWaitReadyWaitReady
A sampled trigger 10 causes a pulse only in Ready. Leaving Pulse unconditionally on the next edge keeps its output high for exactly one clock period, even if a remains high. In Wait, further triggers are ignored until a sampled reset rearms the finite-state machine.
The crucial transition is Pulse --01--> Ready. If reset occurs in the cycle immediately following a trigger, this transition both ends the current pulse and rearms the circuit. The next trigger then produces a pulse after just one intervening low-output cycle. Sending every exit from Pulse to Wait would lose that reset and fail the alternate-cycle requirement. This behavior is explicitly visible in the last three pulses of the original timing diagram.[ref]
For the sixteen sampled pairs in that diagram, numbering the first edge as 1, z is high just after edges and low after every other edge. Equivalently,
The two low-output states cannot be merged: the same future trigger must produce a pulse from Ready and be ignored from Wait. A separate high-output state is needed to hold the one-cycle pulse, explaining the three-state design.

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