Solution

ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2014/digital-systems-linear-algebra-introduction-to-formal-proof/3/b/solution

Let the stored bits be , with most significant. The required Gray code transitions give
Connect directly to the first D flip-flop's data input and feed through one NOT gate to the second input. Drive both enable inputs with and both clock inputs with the same clock. Thus holds both stored bits; takes the next Gray-code counter state at the active clock edge. Reset initializes .
Figure 1.
Enabled Gray-code counter and synchronous SOS sequencer: all stored bits share one clock
. Details.
With ordinary uncomplemented outputs, one NOT gate is minimal: wiring alone cannot produce . If a D flip-flop already provides a complementary output, that output supplies the inversion without an external logic gate. This is a Moore machine because its output depends only on stored state; controls transitions.

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