 Solution

Use $k$ clocked processor registers, each storing an $n$-bit word, two independent combinational read ports and one synchronous write port. Each address requires $a=\lceil {\log }_{2}k\rceil$ bits. The read addresses select two $k$-to-one multiplexers, each $n$ bits wide. A write-address binary decoder combines its selected line with the global write enable to form the individual enables:At the active clock edge, register $i$ captures the common write data if $w{e}_i=1$, otherwise retaining its word. Reads return the currently stored words selected by their respective addresses. For non-power-of-two $k$, unused address codes need a specified harmless implementation. A simultaneous read and write of one address follows the chosen edge/read timing; an additional forwarding circuit would be needed if a different bypass convention were required.