 Solution

Factor the common input before constructing the networks. Use an NMOS transistor controlled by $b$ in series with parallel NMOS transistors controlled by $a$ and $c$. Its conducting condition remains $b(a\vee c)$. The complementary upper network is a PMOS transistor controlled by $b$ in parallel with a series chain of PMOS transistors controlled by $a$ and $c$; its conducting condition is $\neg b\vee \neg a\neg c$.

This is the right panel in part (a). It uses three lower plus three upper transistors, six in total instead of eight, and needs no separate inverter or complemented external input. The complementary CMOS network duality ensures the same static Boolean function and complementary rail connections.