by Ciro Santilli (@cirosantilli, 34)
The problem with a single-level paging scheme is that it would take up too much RAM: 4G / 4K = 1M entries _per_ process.
If each entry is 4 bytes long, that would make 4M _per process_, which is too much even for a desktop computer: ps -A | wc -l says that I am running 244 processes right now, so that would take around 1GB of my RAM!
For this reason, x86 developers decided to use a multi-level scheme that reduces RAM usage.
The downside of this system is that is has a slightly higher access time, as we need to access RAM more times for each translation.

Ancestors (13)

  1. Example: multi-level paging scheme
  2. x86 Paging Tutorial
  3. x86
  4. List of instruction set architectures
  5. Instruction set architecture
  6. Processor (computing)
  7. Computer hardware component type
  8. Computer hardware
  9. Computer
  10. Information technology
  11. Area of technology
  12. Technology
  13. Home

View article source

Discussion (0)

+ New discussion

There are no discussions about this article yet.

Articles by others on the same topic (0)

There are currently no matching articles.
See all articles in the same topic + Create my own version