Born: 1965
Died: 2010+-ish
This is the lowest level of abstraction computer, at which the basic gates and power are described.
At this level, you are basically thinking about the 3D layered structure of a chip, and how to make machines that will allow you to create better, usually smaller, gates.
Video 1. imec: The Semiconductor Watering Hole by Asianometry (2022) Source. A key thing they do is have a small prototype fab that brings in-development equipment from different vendors together to make sure the are working well together. Cool.
What a legendary place.
As mentioned at from Video "Applied Materials by Asianometry (2021)", originally the companies fabs would make their own equipment. But eventually things got so complicated that it became worth it for separate companies to focus on equipment, which then then sell to the fabs.
As of 2020 leading makers of the most important fab photolithography equipment.
Video 1. ASML: TSMC's Critical Supplier by Asianometry (2021) Source.
Video 2. How ASML Won Lithography by Asianometry (2021) Source.
First there were dominant Elmer and Geophysics Corporation of America dominating the market.
Then a Japanese government project managed to make Nikon and Canon Inc. catch up, and in 1989, when Ciro Santilli was born, they had 70% of the market. In 1995, ASML had reached 25% market share. Then it managed the folloging faster than the others:
Parent/predecessor of ASML.
Video 1. Applied Materials by Asianometry (2021) Source. They are chemical vapor deposition fanatics basically.
This is the mantra of the semiconductor industry:
  • power and area are the main limiting factors of chips, i.e., your budget:
    • chip area is ultra expensive because there are sporadic errors in the fabrication process, and each error in any part of the chip can potentially break the entire chip. Although there are
      The percentage of working chips is called the yield.
      In some cases however, e.g. if the error only affects single CPU of a multi-core CPU, then they actually deactivate the broken CPU after testing, and sell the worse CPU cheaper with a clear branding of that: this is called binning,5892.html
    • power is a major semiconductor limit as of 2010's and onwards. If everything turns on at once, the chip would burn. Designs have to account for that.
  • performance is the goal.
    Conceptually, this is basically a set of algorithms that you want your hardware to solve, each one with a respective weight of importance.
    Serial performance is fundamentally limited by the longest path that electrons have to travel in a given clock cycle.
    The way to work around it is to create pipelines, splitting up single operations into multiple smaller operations, and storing intermediate results in memories.
They put a lot of expensive equipment together, much of it made by other companies, and they make the entire chip for companies ordering them.
A list of fabs can be seen at: and basically summarizes all the companies that have fabs.
AMD just gave up this risky part of the business amidst the fabless boom. Sound like a wise move. They then fell more and more away from the state of the art, and moved into more niche areas.
Video 1. SMIC, Explained by Asianometry (2021) Source.
One of the companies that has fabs, which buys machines from companies such as ASML and puts them together in so called "silicon fabs" to make the chips
As the quintessential fabless fab, there is on thing TSMC can never ever do: sell their own design! It must forever remain a fab-only company, that will never compete with its customers. This is highlighted e.g. at from Video "How Nvidia Won Graphics Cards by Asianometry (2021)".
Video 1. How Taiwan Created TSMC by Asianometry (2020) Source. Some points:
  • UCM failed because it focused too much on the internal market, and was shielded from external competition, so it didn't become world leading
  • one of TSMC's great advances was the fabless business model approach.
  • they managed to do large technology transfers from the West to kickstart things off
  • one of their main victories was investing early in CMOS, before it became huge, and winning that market
Basically what register transfer level compiles to in order to achieve a real chip implementation.
After this is done, the final step is place and route.
They can be designed by third parties besides the semiconductor fabrication plants. E.g. Arm Ltd. markets its Artisan Standard Cell Libraries as mentioned e.g. at: This came from a 2004 acquisition:, obviously.
The standard cell library is typically composed of a bunch of versions of somewhat simple gates, e.g.:
  • AND with 2 inputs
  • AND with 3 inputs
  • AND with 4 inputs
  • OR with 2 inputs
  • OR with 3 inputs
and so on.
Each of those gates has to be designed by hand as a 3D structure that can be produced in a given fab.
Simulations are then carried out, and the electric properties of those structures are characterized in a standard way as a bunch of tables of numbers that specify things like:
  • how long it takes for electrons to pass through
  • how much heat it produces
Those are then used in power, performance and area estimates.
Open source ones:
A set of software programs that compile high level register transfer level languages such as Verilog into something that a fab can actually produce. One is reminded of a compiler toolchain but on a lower level.
The most important steps of that include:
The output of this step is another Verilog file, but one that exclusively uses interlinked cell library components.
Given a bunch of interlinked standard cell library elements from the logic synthesis step, actually decide where exactly they are going to go on 2D (stacked 2D) integrated circuit surface.
Sample output format of place and route would be GDSII.
Figure 1. 3D rendering of a GDSII file. Source.
The main ones as of 2020 are:
They apparently even produced a real working small RISC-V chip with the flow, not bad.
Very good channel to learn some basics of semiconductor device fabrication!
Focuses mostly on the semiconductor industry. from Video "SMIC, Explained by Asianometry (2021)" from mentions he is of Chinese ascent, ancestors from Ningbo. Earlier in the same video he mentions he worked on some startups. He doesn't appear to speak perfect Mandarin Chinese anymore though based on pronounciation of Chinese names. gives an abbreviated name "Jon Y".
Video 1. Reflecting on Asianometry in 2022 by Asianometry (2022) Source. Mentions his insane work schedule: 4 hours research in the morning, then day job, then editing and uploading until midnight. Appears to be based in Taipei. Two videos a week. So even at the current 400k subs, he still can't make a living.
It is quite amazing to read through books such as The Supermen: The Story of Seymour Cray by Charles J. Murray (1997), as it makes you notice that earlier CPUs (all before the 70's) were not made with integrated circuits, but rather smaller pieces glued up on PCBs! E.g. the arithmetic logic unit was actually a discrete component at one point.
The reason for this can also be understood quite clearly by reading books such as Robert Noyce: The Man Behind the Microchip by Leslie Berlin (2006). The first integrated circuits were just too small for this. It was initially unimaginable that a CPU would fit in a single chip! Even just having a very small number of components on a chip was already revolutionary and enough to kick-start the industry. Just imagine how much money any level of integration saved in those early days for production, e.g. as opposed to manually soldering point-to-point constructions. Also the reliability, size an weight gains were amazing. In particular for military and spacial applications originally.
Register transfer level is the abstraction level at which computer chips are mostly designed.
The only two truly relevant RTL languages as of 2020 are: Verilog and VHDL. Everything else compiles to those, because that's all that EDA vendors support.
Much like a C compiler abstracts away the CPU assembly to:
  • increase portability across ISAs
  • do optimizations that programmers can't feasibly do without going crazy
Compilers for RTL languages such as Verilog and VHDL abstract away the details of the specific semiconductor technology used for those exact same reasons.
The compilers essentially compile the RTL languages into a standard cell library.
Examples of companies that work at this level include:
In the past, most computer designers would have their own fabs.
But once designs started getting very complicated, it started to make sense to separate concerns between designers and fabs.
What this means is that design companies would primarily write register transfer level, then use electronic design automation tools to get a final manufacturable chip, and then send that to the fab.
It is in this point of time that TSMC came along, and benefied and helped establish this trend.
The term "Fabless" could in theory refer to other areas of industry besides the semiconductor industry, but it is mostly used in that context.
Examples under verilog, more details at Verilator.
Verilog simulator that transpiles to C++.
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.
Some simulation examples under verilog.
First install Verilator. On Ubuntu:
sudo apt install verilator
Tested on Verilator 4.038, Ubuntu 22.04.
Run all examples, which have assertions in them:
cd verilator
make run
File structure is for example:
Example list:
The example under verilog/interactive showcases how to create a simple interactive visual Verilog example using Verilator and SDL.
You could e.g. expand such an example to create a simple (or complex) video game for example if you were insane enough. But please don't waste your time doing that, Ciro Santilli begs you.
Usage: install dependencies:
sudo apt install libsdl2-dev verilator
then run as either:
make run RUN=and2
make run RUN=move
Tested on Verilator 4.038, Ubuntu 22.04.
In those examples, the more interesting application specific logic is delegated to Verilog (e.g.: move game character on map), while boring timing and display matters can be handled by SDL and C++.
Examples under vhdl, more details at: GHDL.
Examples under vhdl.
First install GHDL. On Ubuntu:
sudo apt install verilator
Tested on Verilator 1.0.0, Ubuntu 22.04.
Run all examples, which have assertions in them:
cd vhdl
As of 2020's, it is basically a cheap/slow/simple CPU used in embedded system applications.
It is interpreted. It actually implements a Python (-like ?) interpreter that can run on a microcontroller. See e.g.: Compile MicroPython code for Micro Bit locally.
As a result, it is both very convenient, as it does not require a C toolchain to build for, but also very slow and produces larger images.
The first thing you must understand is the Classic RISC pipeline with a concrete example.
The good:
  • slick UI! But very hard to read characters, they're way too small.
  • attempts to show state diffs with a flash. But it goes by too fast, would be better if it were more permanent
  • Reverse debugging
The bad:
  • educational ISA
  • unclear what flags mean from UI, no explanation on hover. Likely the authors assume knowledge of the Y86 book.
The good:
The bad:
  • Clunky UI
  • circuit diagram doesn't show any state??
It basically replaces a bunch of discrete digital components with a single chip. So you don't have to wire things manually.
Particularly fundamental if you would be putting those chips up a thousand cell towers for signal processing, and ever felt the need to reprogram them! Resoldering would be fun, would it? So you just do a over the wire update of everything.
Vs a microcontroller: same reason why you would want to use discrete components: speed. Especially when you want to do a bunch of things in parallel fast.
One limitation is that it only handles digital electronics: There are some analog analogs, but they are much more restricted due to signal loss, which is exactly what digital electronics is very good at mitigating.
Video 1. First FPGA experiences with a Digilent Cora Z7 Xilinx Zynq by Marco Reps (2018) Source. Good video, actually gives some rationale of a use case that a microcontroller wouldn't handle because it is not fast enough.
Video 2. FPGA Dev Board Tutorial by Ben Heck (2016) Source.
Video 3. The History of the FPGA by Asianometry (2022) Source.
Video 1. The Coming AI Chip Boom by Asianometry (2022) Source.
Our definition of fog computing: a system that uses the computational resources of individuals who volunteer their own devices, in which you give each of the volunteers part of a computational problem that you want to solve.
Folding@home and SETI@home are perfect example of that definition.
Advantages of fog: there is only one, reusing hardware that would be otherwise idle.
  • in cloud, you can put your datacenter on the location with the cheapest possible power. On fog you can't.
  • on fog there is some waste due to network communication.
  • you will likely optimize code less well because you might be targeting a wide array of different types of hardware, so more power (and time) wastage. Furthermore, some of the hardware used will not not be optimal for the task, e.g. CPU instead of GPU.
All of this makes Ciro Santilli doubtful if it wouldn't be more efficient for volunteers simply to donate money rather than inefficient power usage.
Figure 1. Cloud Computing market share in Q2 2022 by Source.
Basically means "company with huge server farms, and which usually rents them out like Amazon AWS or Google Cloud Platform
Figure 1. Global electricity use by data center type: 2010 vs 2018. Source. The growth of hyperscaler cloud vs smaller cloud and private deployments was incredible in that period!