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An analog switch uses a control signal to connect or disconnect an analog signal path. The control chooses the conducting state; the transmitted electric potential difference is not restricted to a binary logic value. Real devices have finite analog switch on-resistance, leakage and parasitic capacitance. The primary tutorial describes a bilateral CMOS switch formed from complementary transistors.^[ref]

For an original loading example, connect an ideal $1\mathrm{V}$ source through a stipulated $100\Omega$ on-resistance to a $10\mathrm{k\Omega }$ load. The output isThe closed switch therefore changes the amplitude even before any switching transient is considered. This is a chosen resistor model, not a specification for a particular part. Variation of on-resistance with signal level can additionally produce distortion.

An open switch is also not an ideal infinite impedance. For example, a stipulated $10\mathrm{nA}$ analog switch leakage current into $100\mathrm{pF}$ changes the node potential at $I/C=100V/s$, or $0.10\mathrm{V}$ in a millisecond if that model remains valid. A high-impedance measurement can be sensitive to this small current.

On a bench, compare the transmitted level and the open-state drift with the same source, load and oscilloscope conditions. Analog switch charge injection concerns the control transition itself, while settling time concerns how long the complete circuit needs to approach its final value. Those effects are separate from the static conducting-state error.

The leakage-limited hold time is the duration for which a stored electric potential difference remains within a stated drift allowance when unwanted electric current changes the stored electric charge. For a constant net leakage $I_{\mathrm{leak}}$ into a fixed capacitance $C$,An allowed drift $\epsilon >0$ therefore gives $T_{\max }=C\epsilon /|I_{\mathrm{leak}}|$. This is a limit from a specified error mechanism, not the complete accuracy or usable duration of an instrument. The ACF2101 datasheet identifies amplifier bias, capacitor leakage and switch leakage as separate contributions to droop.^[ref]

For an original example, a4.7nanofarad capacitor,50picoamperes of net leakage and a0.20millivolt drift allowance giveIf the readout adds a further30picoamperes in the same direction, the correct total is80picoamperes and the duration falls to11.75milliseconds. The relevant electric current is the sum of all paths at the stored node, not necessarily the isolated analog switch leakage current specification.

For time-dependent leakage, the exact charge balance isA verified bound $|I_{\mathrm{net}}(t)|\le I_{\max }$ guarantees $|\Delta v(T)|\le I_{\max }T/C$. Oppositely signed contributions can cancel at one operating point without providing that bound elsewhere. Temperature, terminal potentials and board leakage must match the intended operating conditions.^[ref]

A bench check records the held node at several delays after the switching transient, using a known total capacitance and a readout whose input current is included in the model. The slope estimates net leakage. A step created at the transition is analog switch charge injection, not steady droop. If the initial step already uses part of a total error allowance, only the remaining allowance is available for calculating the leakage-limited hold time.