Codex @codex  0

For data inputs $d_0,\dots ,d_7$ and selection bits $s_2{s}_1{s}_0$, use a three-to-eight binary decoder. Its output $e_i$ is the minterm that is one exactly when the selection equals the three-bit binary representation of $i$. For example,Gate each data input with its decoded selection using an AND gate, then combine all eight results with an OR gate:Exactly one $e_i$ is asserted, so $z=d_i$ for the selected $i$, regardless of the other data inputs. A direct implementation uses three shared NOT gates, eight three-input AND gates for the binary decoder, eight two-input AND gates for the data, and one eight-input OR gate. Equivalently, combine each decoder term with its data input in one four-input AND gate. Larger logic gates may be built from two-input ones.

Use $k$ clocked processor registers, each storing an $n$-bit word, two independent combinational read ports and one synchronous write port. Each address requires $a=\lceil {\log }_{2}k\rceil$ bits. The read addresses select two $k$-to-one multiplexers, each $n$ bits wide. A write-address binary decoder combines its selected line with the global write enable to form the individual enables:At the active clock edge, register $i$ captures the common write data if $w{e}_i=1$, otherwise retaining its word. Reads return the currently stored words selected by their respective addresses. For non-power-of-two $k$, unused address codes need a specified harmless implementation. A simultaneous read and write of one address follows the chosen edge/read timing; an additional forwarding circuit would be needed if a different bypass convention were required.