Bus burst 2026-10-13
A group of related payload transfers, often to consecutive addresses, arranged under one transfer sequence. A bus burst can amortize setup and bus arbitration overhead; a longer period of exclusive bus ownership can also make another initiator wait longer. The exact overhead and permitted handover boundaries depend on the protocol.[ref]
Bus contention 2026-10-13
Here, competition between pending initiators for the same shared computer bus resource. Correct bus arbitration converts this competition into waiting. Simultaneously driving incompatible values on the same electrical lines is a different, erroneous kind of bus contention; multiple pending requests need not cause it.
Computer bus 2026-10-13
A computer bus connects components through agreed communication paths and transfer rules. On a shared computer bus, a CPU and a DMA engine can both want the same path to computer memory: attaching another initiator does not create another independent path. Bus arbitration chooses who may start; bus ownership states who may use each resource; bus throughput measures the useful data delivered. This makes sharing a performance question as well as a correctness question.
Figure 1.
Shared computer bus paths, bus arbitration, and address, data and control roles
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Control bus 2026-10-13
The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.[ref]
Shared-bus timing example 2026-10-13
Consider a stipulated synchronous shared computer bus, rather than a timing claim about any named hardware protocol. Assume a 32-bit data bus, a 100 MHz clock, and one four-byte payload transfer per bus cycle during the data phase. Both initiators and request at time zero. has one four-transfer write bus burst and one two-transfer write bus burst, to an immediately ready target in computer memory. Each bus burst pays one bus cycle for bus arbitration and one for its starting address and command; subsequent addresses advance implicitly. The arbiter chooses first, owners finish their entire bus bursts, and no phases overlap. There are no bus wait states, retries, extra completion cycles, direction changes or intervening requests. Payload is counted when each data phase completes; the observation interval starts at the first bus arbitration cycle and ends at the last payload completion.
Figure 1.
Stipulated bus arbitration and payload timing for two competing bus bursts
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A bus cycle lasts
The timeline uses half-open intervals of bus cycles: has bus arbitration on , address and command on , and four payload transfers on . Then has bus arbitration on , address and command on , and two payload transfers on . Their final payload completions are at 60 ns and 100 ns respectively. waits 60 ns before its own selection cycle even though both requests arrived together.
The six payload transfers contain 24 bytes. Ten bus cycles take 100 ns, giving finite-interval bus throughput
where MB means bytes. The raw data bus rate is . Payload occupies of the interval. If this same pair repeats with no gaps, its long-run bus throughput equals the finite-interval value; isolated observations need not predict a later workload.
Reverse the bus arbitration order, keeping these assumptions. finishes after four bus cycles, at 40 ns; finishes at 100 ns. Aggregate bus throughput stays 240 MB/s, but 's request-to-completion time falls from 100 ns to 40 ns and 's rises from 60 ns to 100 ns. Scheduling changes who waits without changing the available payload capacity in this example.
For an independent perturbation, retain first and add two bus wait states before 's final payload transfer. The interval grows to 120 ns with the same 24 bytes, so bus throughput falls to 200 MB/s. For another workload, one initiator sends all six transfers in a single bus burst: the stipulated overhead is paid once, giving eight bus cycles, 80 ns and 300 MB/s. This latter comparison assumes one combined request is valid; combining different initiators' operations is not automatically permitted.