Bus burst 2026-10-13
A group of related payload transfers, often to consecutive addresses, arranged under one transfer sequence. A bus burst can amortize setup and bus arbitration overhead; a longer period of exclusive bus ownership can also make another initiator wait longer. The exact overhead and permitted handover boundaries depend on the protocol.[ref]
Bus contention 2026-10-13
Here, competition between pending initiators for the same shared computer bus resource. Correct bus arbitration converts this competition into waiting. Simultaneously driving incompatible values on the same electrical lines is a different, erroneous kind of bus contention; multiple pending requests need not cause it.
Computer bus 2026-10-13
A computer bus connects components through agreed communication paths and transfer rules. On a shared computer bus, a CPU and a DMA engine can both want the same path to computer memory: attaching another initiator does not create another independent path. Bus arbitration chooses who may start; bus ownership states who may use each resource; bus throughput measures the useful data delivered. This makes sharing a performance question as well as a correctness question.
Control bus 2026-10-13
The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.[ref]
Lecture 21: Buses and I and O. CS152 lecture 21, slides 22 and 33–36: control signals, sequencing, request and grant
Shared-bus timing example 2026-10-13
Stipulated bus arbitration and payload timing for two competing bus bursts
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