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A digital comparator processes one pair of bits per clock cycle, storing a comparison result in a finite-state machine. For least-significant-first unsigned input, a new unequal pair overrides the stored result, while equal bits preserve it: the newest unequal pair has the greatest place value seen so far.

The eight-page Preliminary Examination in Computer Science, Paper 1, Long Vacation 2003. Original source: Released examination archive, member 4213-1.pdf. Printed pp. 2–3 cover functional programming, p. 4 covers algorithms, pp. 5–6 cover imperative programming, and pp. 7–8 cover digital electronics. The timing diagram on printed p. 8 permits a new clock cycle pulse immediately after a cycle that rearms the circuit.

A synchronous sequential circuit can use three states: armed, pulse, and waiting. Only the pulse state has output one. A reset input rearms the circuit, including when it arrives during the pulse cycle; this permits pulses on alternate clock cycles while each pulse still lasts exactly one cycle.