Digital electronics represents information by discrete signal levels. Combinational logic computes from current inputs; sequential logic also uses stored state.
A recurring digital signal whose designated clock edge triggers a state update. A rising clock edge is the transition from the low level to the high level; a falling clock edge is the reverse.
The reciprocal of the processor clock period. Reducing a combinational critical path can permit a higher frequency, subject to the remaining timing requirements.
The interval between successive designated clock edges of a processor's clock signal. In a synchronous sequential circuit it must be long enough for the required register-to-register propagation and setup timing.
A circuit producing a periodic output at an integer fraction of the input frequency. Each toggle stage divides the triggering frequency by two, so stage in an -stage binary ripple counter has ideal output frequency .
A sequential circuit has stored state. Its future output can therefore depend on earlier inputs as well as the present inputs.
A directed graph with one vertex for each state and labelled edges for the permitted transitions. A finite counter has a directed cycle when every state has one successor.
A counter stores a binary representation of a state, usually advancing by one increment or decrement modulo when it has bits.
A cascade in which an output transition of one flip-flop clocks the next. With positive-edge-triggered toggle stages and uncomplemented connections, it decrements modulo : a zero bit rises to one and propagates a borrow, while a one bit falls to zero and stops propagation. Ripple propagation takes time, so intermediate transient states are not the settled counter state.
A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.
The data input must remain stable for a specified interval before the sampling clock edge and a specified interval after it. Violations can prevent a well-defined sampled bit.
A control that resets stored state independently of the clock edge. An active-low clear is asserted by a low signal; clocked sampling resumes after the clear is released.
At the active clock edge, . An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.
At the active clock edge, the next state is : inputs hold, reset, set, and toggle. In particular, gives , whereas gives . The standard function table is illustrated by a positive-edge device in the [ref]. Its asynchronous reset is active high; another circuit may specify an active-low clear.
