Digital electronics represents information by discrete signal levels. Combinational logic computes from current inputs; sequential logic also uses stored state.
A digital circuit implementing binary multiplication. A combinational logic implementation forms shifted partial products with AND gates and combines them with adders. A sequential circuit can instead reuse one adder, storing a partial sum, a shifted multiplicand, and the remaining multiplier in digital registers. If those quantities are , the update , , preserves . Starting with and stopping when therefore produces , provided widths prevent overflow.
A temporary excursion of an output logic signal to its active level. A clocked controller may specify the duration in complete clock periods, rather than relying on an analogue delay.
A display whose seven separately controlled bars can form digit shapes. A combinational logic decoder maps an encoded digit to seven output bits. Active-high versus active-low control and the required behaviour for unused input codes belong to the decoder's specification.
Represent a decimal number by coding each decimal digit separately as four bits of weights . The codes 10–15 are unused for one digit; a Boolean circuit must specify whether these combinations produce a defined result or are don't-care conditions.
An arbiter selects at most one asserted request, searching cyclically after the most recent successful recipient. After a grant it advances that remembered position. This implements circular priority among bits representing competing requests; it is distinct from assigning a fixed priority forever.
Store both the last recipient index and a current-grant valid bit . With possible recipients, an idle period clears while preserving . The Moore machine grants requester precisely when holds. For , its idle states are distinguishable by a subsequent pair of competing requests with different positions in the cyclic order; active states have distinct outputs. Thus all states are distinguishable and state bits suffice and are necessary for this output convention. A continuously asserted request receives a grant within decisions, because before that grant the cyclic scan cannot pass it to choose a later asserted request.
A recurring digital signal whose designated clock edge triggers a state update. A rising clock edge is the transition from the low level to the high level; a falling clock edge is the reverse.
One complete repetition of a periodic clock signal, for example from one rising clock edge to the next. Its duration is the clock period. A synchronous sequential circuit can update its stored state once per designated clock edge; a one-cycle output pulse remains asserted for one such interval.
The time between equivalent clock edges in consecutive cycles of a periodic clock signal. It is the reciprocal of the clock's frequency.
The reciprocal of the processor clock period. Reducing a combinational critical path can permit a higher frequency, subject to the remaining timing requirements.
The interval between successive designated clock edges of a processor's clock signal. In a synchronous sequential circuit it must be long enough for the required register-to-register propagation and setup timing.
A circuit producing a periodic output at an integer fraction of the input frequency. Each toggle stage divides the triggering frequency by two, so stage in an -stage binary ripple counter has ideal output frequency .
A sequential circuit has stored state. Its future output can therefore depend on earlier inputs as well as the present inputs.
An electronic display cycling through the six die faces while a switch is pressed. A modulo-six counter and combinational logic can drive seven lights arranged as die pips. The apparent unpredictability comes from uncertainty in release timing relative to a rapid clock signal; deterministic cycling alone does not establish equal outcome probabilities.
A fixed-width collection of flip-flops storing a binary representation. A synchronous load-enabled digital register captures all its input bits on the active clock edge when load is asserted and otherwise retains its old value. One multiplexer before each D flip-flop can select new data or feedback from its old output. A processor register is a particular use inside a processor; temporary state in a standalone binary multiplier is another.
A chain of digital registers that transfers each stored value to the next stage at a clock edge. A serial-in parallel-out shift register exposes the stored history simultaneously. With the current input and delayed samples, combinational logic can evaluate a function of the latest samples.
A shift register accepting one sample at each clock edge and exposing every stored stage as a parallel output.
A directed graph with one vertex for each state and labelled edges for the permitted transitions. A finite counter has a directed cycle when every state has one successor.
A counter stores a binary representation of a state, usually advancing by one increment or decrement modulo when it has bits.
A digital counter cycling through six stored values. With ordinary binary representation, the valid three-bit states are . The unused encodings require either an initialization assumption or specified recovery transitions.
A cascade in which an output transition of one flip-flop clocks the next. With positive-edge-triggered toggle stages and uncomplemented connections, it decrements modulo : a zero bit rises to one and propagates a borrow, while a one bit falls to zero and stops propagation. Ripple propagation takes time, so intermediate transient states are not the settled counter state.
A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.
The time from a triggering clock edge to the corresponding settled output of a flip-flop, under specified loading. The time available between successive active clock edges must accommodate this delay, the combinational critical path, the receiving flip-flop's setup time, and any clock uncertainty.
The data input must remain stable for a specified interval before the sampling clock edge and a specified interval after it. Violations can prevent a well-defined sampled bit.
The minimum interval after an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains how quickly a newly launched value may reach the receiving flip-flop.
The minimum interval before an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains the latest arrival of new data at the receiving flip-flop.
A control that resets stored state independently of the clock edge. An active-low clear is asserted by a low signal; clocked sampling resumes after the clear is released.
At the active clock edge, . An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.
At the active clock edge, the next state is : inputs hold, reset, set, and toggle. In particular, gives , whereas gives . The standard function table is illustrated by a positive-edge device in the [ref]. Its asynchronous reset is active high; another circuit may specify an active-low clear.
