Coordinating CPU and device access to a DMA buffer, including any required memory cache maintenance and ordering. A completed device write must be made visible before the CPU consumes it. The Linux kernel distinguishes coherent mappings from streaming mappings needing synchronization at ownership changes; even coherent mappings can require ordering of writes. [ref]
https://docs.kernel.org/core-api/dma-api-howto.html. Linux kernel documentation, Dynamic DMA mapping Guide: types of DMA mappings and using streaming DMA mappings
[ref]https://docs.kernel.org/core-api/dma-api.html. James E. J. Bottomley, Linux DMA API, part Ia: coherent buffers and write ordering
Articles by others on the same topic
There are currently no matching articles.