A particularly transparent design uses six D flip-flops in a one-hot encoding. Let mean that face is displayed. Initialize and , and wire the next-state inputs as a ring:
All six D flip-flops share the same active clock edge. Each pulse moves the single stored to the next position, giving the state-transition diagram cycle . The representation invariant “exactly one is high” holds after initialization and is preserved by rotation. Six D flip-flops are more than the three-bit theoretical minimum, but their simple wiring gives a complete implementation without requiring that minimum.
Figure 1.
One-hot ring state register and the six lamp patterns, including the original opposite diagonals on faces 2 and 3
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Decode the seven lamps by their positions, with denoting top, middle and bottom, and denoting left and right. Let be the center lamp. In the original figure, face 2 uses top-left and bottom-right, while face 3 uses top-right and bottom-left plus center; the two diagonals must therefore have different controls.[ref] The required OR gate decoder is
For example, only the center is high in state , the first diagonal is high in state , and in state both outer columns are high while the center is low. This verifies all six layouts directly.
To implement the switch behavior, use a rapid common clock signal and a sampled enable , high while the switch is pressed. Each next-state input is then selected between its advancing value and its own stored value:
One multiplexer per D flip-flop implements that selection. While enabled the electronic dice advances; otherwise every D flip-flop reloads its own value and the display holds. The enable supplied to this synchronous design must be stable at sampling edges. A reset or preset facility must establish the specified one-hot initial state: an all-zero ring does not start itself.
With a rapid clock signal, uncertainty in human release timing makes the final face practically unpredictable. The sequential circuit itself is deterministic; this observation alone is not a proof that its six outcomes have equal probabilities.
Use function extensionality: show for every value of the argument type. In lazy evaluation semantics, “every value” includes the bottom value and partial values. For list arguments, structural induction on lazy lists supplies the empty, bottom and cons cases, with continuity justifying passage to infinite lists.
The original printed equation has the same right fold on both sides, including the same operator and seed; this is visible in the scan.[ref] Thus its literal answer is
For every input , both sides denote the very same expression foldr (oplus) e xs; equality follows by reflexivity. This remains true if its value is . Neither termination nor associativity nor an identity law is required. The scan does not establish a different intended equation, so no replacement by a left fold is assumed.
The printed word “even” conflicts with the displayed numbers: all ten listed prime numbers are odd, and is the only even prime number. The scan confirms that wording.[ref] We first construct the detector for the explicitly listed numbers, then add as requested. The literal even-prime detector is also given below.
Let the five input bits be with value . Every listed number has . For that plane, the four-variable Karnaugh map is
The entire plane is zero. Five valid groups in the displayed Karnaugh map give the product terms
Including , their accepted numbers are respectively , , , , and . Their union is exactly the ten listed numbers. Hence an explicit Boolean circuit is: invert where needed, feed the five products into five AND gates, combine those outputs with an OR gate, and AND with . Its output is
Any gate with more than two inputs can be replaced by a tree of two-input gates. To include the exceptional prime number , detect its exact binary representation and add one OR branch:
If “even prime” is read literally instead of following the listed numbers, the complete first detector is simply
All three formulas classify all possible inputs, including and as nonprime.