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A gate-normalized detector output reports an integrated detector signal divided by the duration of the detection time gate. For an input electric potential difference waveform $v(t)$ and a gate from $t_0$ to $t_0+T_g$, the input-referred average isIts units are those of electric potential difference, whereas the integral has units of electric potential difference times time. The SR250 gated integrator implements integration followed by gate-width normalization and an adjustable amplification stage.^[ref]

For an original idealized detector pulse, take $v(t)=2\mathrm{mV}$ from0 to4nanoseconds and zero outside that interval. A gate covering0–4nanoseconds integrates $8\mathrm{mV}\mathrm{ns}$ and reports an average of2millivolts. A gate covering0–8nanoseconds integrates the same area but reports1millivolt. Thus unchanged admitted pulse area need not give an unchanged normalized output.

The gate average also differs from the average over a full repetition period. For the same pulse repeated once per microsecond, the full-period mean is only8microvolts. Comparing instruments therefore requires knowing whether the reported quantity is pulse area, within-gate average or full-period average.

A constant baseline $b$ contributesGate-width normalization does not remove that baseline. A separate reference or subtraction measurement is needed to distinguish it from the desired signal.

An apparatus check overlays the gate monitor and detector waveform on an oscilloscope, then varies the gate width while keeping its start fixed. A flat plateau should retain its input-referred average while the gate remains inside it; a short pulse diluted by additional quiet time behaves like the example above. Gate timing jitter and gate-width jitter can alter which signal portion is admitted and which duration is used for normalization.^[ref]

Gate timing jitter is shot-to-shot variation in the timing of a detection time gate relative to the signal being measured. It differs from a fixed delay error: repeated gates may have the correct mean delay while admitting different portions of a rapidly varying detector signal. The SR250 catalogue describes a trigger-controlled gate, finite delay jitter and a gate-monitor output that can be overlaid with the signal on an oscilloscope.^[ref]

For an original sensitivity derivation, let a reproducible baseline-corrected electric current waveform be $i(t)$ and the intended integrated electric charge beSmall edge errors giveIf both edges shift by the same amount, the gate width is unchanged butThus a gate translating within a flat plateau has little first-order sensitivity, while a gate whose edges intersect different signal levels can be sensitive even at fixed width.

For stipulated edge currents $i(t_0)=100\mathrm{nA}$ and $i(t_1)=20\mathrm{nA}$, a common timing error with standard deviation $2\mathrm{ns}$ contributes approximately $0.16\mathrm{fC}$ charge standard deviation. This calculation assumes smooth waveform values near both edges and timing excursions small enough for linearization. A gate crossing an abrupt onset requires the actual waveform integral.

Gate-width jitter is a separate effect. For a constant plateau current $I$, $Q=I(t_1-t_0)$, so $\delta Q=I\delta T_g$ even though a common gate translation would cancel. More generally, the edge-error contribution has varianceThe covariance determines whether two individually noisy edges largely preserve the width.

An apparatus check records both the gate monitor and signal waveform over many triggers, using the same time reference, to estimate relative delay and width distributions. A single aligned trace establishes neither distribution. Timing motion shared by the pulse and gate can cancel in their relative delay; the uncertainty relevant to the measured charge is their relative timing, not solely a gate generator's standalone specification.