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Analog switch leakage current is unwanted electric current at an analog switch's signal terminals under stated terminal potentials, switch state and temperature. It can produce a steady offset in a resistive load or accumulate electric charge on an isolated capacitor. The manufacturer's equivalent circuits distinguish on-state and off-state leakage paths; their effects depend on the external circuit.^[ref]

For an original chosen model, let a constant $20\mathrm{pA}$ enter a node with a $50\mathrm{M\Omega }$ resistor to a reference. The steady electric potential difference error is $IR=1.0\mathrm{mV}$. Replacing that load by an initially isolated $200\mathrm{pF}$ capacitor instead givesA $100\mu \mathrm{V}$ drift allowance is exhausted in $1.0\mathrm{ms}$. This leakage-limited hold time assumes constant leakage and capacitance; it ceases to apply if the changing node potential substantially changes the leakage. With both the resistor and capacitor present, $Cdv/dt=I_{\mathrm{leak}}-v/R$ approaches the steady error exponentially.

To measure the effect, hold the switch control fixed, disconnect the intended signal current and record the stored-node slope with known total capacitance. Repeat for relevant terminal potentials and temperatures. Readout input current and board leakage must be included in the measurement model. A one-time step at a control transition instead suggests analog switch charge injection; a sustained slope after that step is a different error mechanism.

The leakage-limited hold time is the duration for which a stored electric potential difference remains within a stated drift allowance when unwanted electric current changes the stored electric charge. For a constant net leakage $I_{\mathrm{leak}}$ into a fixed capacitance $C$,An allowed drift $\epsilon >0$ therefore gives $T_{\max }=C\epsilon /|I_{\mathrm{leak}}|$. This is a limit from a specified error mechanism, not the complete accuracy or usable duration of an instrument. The ACF2101 datasheet identifies amplifier bias, capacitor leakage and switch leakage as separate contributions to droop.^[ref]

For an original example, a4.7nanofarad capacitor,50picoamperes of net leakage and a0.20millivolt drift allowance giveIf the readout adds a further30picoamperes in the same direction, the correct total is80picoamperes and the duration falls to11.75milliseconds. The relevant electric current is the sum of all paths at the stored node, not necessarily the isolated analog switch leakage current specification.

For time-dependent leakage, the exact charge balance isA verified bound $|I_{\mathrm{net}}(t)|\le I_{\max }$ guarantees $|\Delta v(T)|\le I_{\max }T/C$. Oppositely signed contributions can cancel at one operating point without providing that bound elsewhere. Temperature, terminal potentials and board leakage must match the intended operating conditions.^[ref]

A bench check records the held node at several delays after the switching transient, using a known total capacitance and a readout whose input current is included in the model. The slope estimates net leakage. A step created at the transition is analog switch charge injection, not steady droop. If the initial step already uses part of a total error allowance, only the remaining allowance is available for calculating the leakage-limited hold time.