This is Ladner's theorem. Assume and let be the Boolean satisfiability problem. Enumerate all clocked polynomial-time deterministic machines as and all clocked polynomial-time candidate reductions as . A standard delayed-diagonalization schedule gives a nondecreasing, unbounded, polynomial-time computable function that increases only by one. Define
The schedule alternates two requirements. At even stage , it holds fixed while searching successively larger finite sets of strings for an on which disagrees with membership in ; after finding one it increments . At odd stage , it searches for an such that
and then increments . Length and simulation budgets are increased slowly enough that each finite search is eventually exhaustive but computing still takes polynomial time. This is achieved, for example, by permitting only simulation steps and searches on strings of logarithmic length before deciding .
Every stage must finish. If an even stage remained forever, then would eventually be a fixed even number, so and would differ on only finitely many strings. If decided , those finitely many exceptions could be hardwired to decide in P, contradicting . If an odd stage remained forever, then would eventually be odd and would be finite. A correct polynomial-time many-one reduction from to would again put in P. Thus every fails to decide , and every fails to reduce to .
Finally, : compute and, when it is even, use the usual polynomial-time certificate for satisfiability. Hence
The problem belongs to NP: an assignment in is a polynomial-length certificate in computational complexity, and substitution verifies every equation in polynomial time.
For NP-hardness, reduce the Circuit satisfiability problem. Introduce one variable in for every wire of a Boolean circuit. A logical negation gate is enforced by , and a logical conjunction gate is enforced by . For a logical disjunction gate use the suggested quadratic equation
which is equivalent to for bits . Add the linear equation for the designated output wire.
The construction introduces one variable and one equation per wire or gate, so it is a polynomial-time many-one reduction. A satisfying circuit input extends uniquely through its gates to a solution of the equations, and any solution gives a consistent accepting circuit computation. Since circuit satisfiability is NP-complete, quadratic-equation satisfiability over F2 is therefore

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