Past exam of the MPhil in micro- and nanotechnology enterprise course of the University of Cambridge / 2018 / Paper 1 / Section B / 8 / iii

Replace one-wire discovery and bespoke alignment with reproducible placement, uniform device geometry and a scalable interconnect process. A circuit needs wires at known sites and orientations with controlled diameter, channel length, composition and electrical properties. Directed assembly, transfer or patterned growth can address placement, but must be validated for occupancy and alignment yield.

Use aligned array patterning rather than locating every randomly deposited wire individually. Control contact resistance, dielectric continuity and gate overlap across the wafer. Plan dielectric isolation, crossovers, vias and multiple interconnect levels so that connections do not short neighboring gates or channels. A reliable supply of the required device polarities and threshold voltages is also needed for the intended logic architecture.

Circuit manufacture additionally requires contamination control, compatible thermal budgets, passivation, dimensional and electrical metrology, defect detection, test structures and repair or redundancy strategies where appropriate. Serial electron-beam writing is useful for prototypes but can become a throughput bottleneck; scalable optical or imprint-based pattern transfer is attractive when its alignment and resolution meet the design. A successful isolated transistor does not establish circuit-level yield or reliability.