Past exam of the MPhil in micro- and nanotechnology enterprise course of the University of Cambridge / 2018 / Paper 1 / Section B / 8

A useful scale estimate is $d\sim k_1\lambda /\mathrm{NA}$, where $\mathrm{NA}=n\sin \alpha$. Five complementary developments are immersion optics, illumination shaping, phase-shifting masks, computational proximity correction and multiple patterning. They address different parts of the process rather than repeal diffraction.

Immersion lithography raises numerical aperture by putting a compatible high-index liquid between the final lens and wafer. Off-axis, annular or dipole illumination places useful diffraction orders within the projection pupil and improves contrast for selected pattern directions.

A phase-shift mask uses controlled optical phase differences to sharpen destructive interference around selected features. Optical proximity correction modifies mask edges and adds assist features to compensate pattern-dependent image formation, resist and etch biases.

Multiple patterning divides a dense final layout into more widely spaced optical patterns, or uses spacer-based pitch division after an optical definition step. Overlay, etch control and pattern decomposition are then critical. For example, with $\lambda =193\mathrm{nm}$, $\mathrm{NA}=1.35$ and $k_1=0.25$, a single-exposure scale is roughly $36\mathrm{nm}$; obtaining dense features of order $20\mathrm{nm}$ commonly requires pitch multiplication rather than attributing everything to one exceptionally sharp aerial image.

These resolution enhancements also require suitable resist contrast, focus control and metrology. The manufacturer's description explains the numerical-aperture benefit of immersion; no claim about a particular 2018 production process is inferred from its current product pages.^[ref]

Locate an isolated nanowire first, then align source, drain, dielectric and top-gate patterns to it. A suitable research-device sequence is the following; the semiconductor is unspecified, so contact-barrier and surface-cleaning details cannot be assumed universally ohmic.

Prepare a clean electrically insulating substrate, with alignment marks. Disperse a sparse population of nanowires from the suspension, remove the carrier solvent compatibly, and locate a suitable isolated wire by microscopy. Record its position relative to the marks.

Use aligned electron beam lithography and a suitable lift-off process to open contact regions near the two ends while leaving a central channel. Clean the exposed contact regions without destroying the wire, evaporate gold and lift off. The contacts overlap the ends but do not bridge the central channel; test their electrical behavior before assuming an ohmic response.

In a second aligned pattern, define a central dielectric patch that extends beyond the proposed gate edges. Evaporate the specified silicon monoxide and lift off using a profile that permits film separation. Verify coverage over the wire and absence of pinholes: directional deposition onto curved nanoscale geometry is not automatically conformal.

Define and evaporate a gold top gate over that insulated central patch, with its lead kept electrically separated from the source, drain and wire. Lift off and test gate leakage before extracting transistor characteristics. The dielectric must remain continuous under the gate and overlap its edges; the illustrated central gate is not a third direct metal contact to the semiconductor. Gold and silicon monoxide are used as stipulated, without silently replacing SiO by a different oxide.

Replace one-wire discovery and bespoke alignment with reproducible placement, uniform device geometry and a scalable interconnect process. A circuit needs wires at known sites and orientations with controlled diameter, channel length, composition and electrical properties. Directed assembly, transfer or patterned growth can address placement, but must be validated for occupancy and alignment yield.

Use aligned array patterning rather than locating every randomly deposited wire individually. Control contact resistance, dielectric continuity and gate overlap across the wafer. Plan dielectric isolation, crossovers, vias and multiple interconnect levels so that connections do not short neighboring gates or channels. A reliable supply of the required device polarities and threshold voltages is also needed for the intended logic architecture.

Circuit manufacture additionally requires contamination control, compatible thermal budgets, passivation, dimensional and electrical metrology, defect detection, test structures and repair or redundancy strategies where appropriate. Serial electron-beam writing is useful for prototypes but can become a throughput bottleneck; scalable optical or imprint-based pattern transfer is attractive when its alignment and resolution meet the design. A successful isolated transistor does not establish circuit-level yield or reliability.