Past exam of the year 1 of the computer science course of the University of Oxford / 2016 / Digital systems, linear algebra, introduction to formal proof (resit) / 1 / c / Solution

Use $w,x,y$ as the three select bits of the 8-to-1 multiplexer, so address $i=4w+2x+y$ selects data input $D_i$. ConnectA single NOT gate produces $\bar{z}$, shared by $D_0$ and $D_3$; the other connections are wires and constant logic levels. For each fixed select address the data input reproduces the corresponding two rows of the truth table, including zeros for all invalid codes.