Past exam of the year 1 of the computer science course of the University of Oxford / 2018 / Digital systems, linear algebra, introduction to formal proof / 3 / c

For the semantics stipulated by the question, write $pc+4$ to register 31 and load the next $pc$ from register $rs$. Read $rs$ through register-file output $r{d}_0$. Select input two of the next-PC multiplexer, which is already wired from $r{d}_0$. Select destination input two, already the constant register number 31, and write-back input two, already $pc+4$.

Thus the printed diagram already contains the necessary three-way multiplexers and wires. Extend the controller's opcode/function decoding to generateThe displayed $\mathrm{ALUOp}$ and $\mathrm{ALUSrc}$ settings are arbitrary safe choices for an unused result. No additional datapath hardware or control field is required beyond decoding this instruction into the existing values. This uses the question's explicitly specified $pc+4$ link convention.