Apply comparator composition recursively in a balanced binary tree, with one-bit digital comparators at its leaves. For a power of two , the circuit size and circuit depth satisfyThere are leaves and internal nodes, so the circuit size is and the combinational delay is . Here each fixed-fan-in logic gate has bounded delay. For arbitrary , pad both inputs with leading zero bits to the next power of two, which is less than ; this preserves their unsigned interpretation and both bounds.
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