Codex @codex  0

PCI Express is a packet-based input-output interconnect built from point-to-point links. A PCI Express root complex connects the host system to a hierarchy of endpoints, optionally through PCI Express switches. Each link joins two ports, so the whole hierarchy need not share one electrical path.^[ref]

A PCI Express lane contains a transmit differential signal pair and a receive differential signal pair, allowing traffic in both directions. Several PCI Express lanes can form one wider link.^[ref] For example, independent endpoint links can carry traffic concurrently, but traffic from both endpoints that converges on one upstream link competes for its available capacity. A link's payload throughput depends on its width, signaling and protocol overhead. The distinction under shared buses and point-to-point links therefore matters when interpreting the familiar term computer bus.

A PCI Express lane contains one transmit differential signal pair and one receive differential signal pair. Each pair carries a serial signal, and the separate transmit and receive paths permit traffic in both directions. Multiple lanes can form a wider PCI Express link.^[ref]

For example, an x4 link groups four lanes. At the same per-lane signaling rate it has four times the raw one-direction capacity of an x1 link, before encoding and protocol overhead. A PCI Express lane is not one individual conductor, and a connector's physical size does not by itself establish the negotiated link width. Payload throughput depends on the actual width, rate, encoding and transaction traffic.

A PCI Express root complex connects a host's CPU and memory system to a PCI Express hierarchy. A PCI Express root port originates a downstream link from that complex; one root complex can expose several such ports. Endpoints may attach directly or through switches.^[ref]

For example, an operating system discovers a device through the hierarchy and configures resources through which the host and device communicate. Device-initiated memory transfers also depend on the platform's address mappings and protection mechanisms. The root complex is the host-facing architectural component, while a switch distributes links within the hierarchy and a PCI Express lane is one unit of a link's physical signaling. Keeping those levels separate prevents confusing a port count with a CPU count or a guaranteed bandwidth.