 Verilator

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Ciro Santilli 34  Updated 2024-12-15  +Created 1970-01-01

Verilog simulator that transpiles to C++.

One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.

Some simulation examples under verilog.

First install Verilator. On Ubuntu:

sudo apt install verilator

Tested on Verilator 4.038, Ubuntu 22.04.

Run all examples, which have assertions in them:

cd verilator
make run

File structure is for example:

verilog/counter.v: Verilog file
verilog/counter.cpp: C++ loop which clocks the design and runs tests with assertions on the outputs
verilog/counter.params: gcc compilation flags for this example
verilog/counter_tb.v: Verilog version of the C++ test. Not used by Verilator. Verilator can't actually run out _tb files, because they do in Verilog IO things that we do better from C++ in Verilator, so Verilator didn't bother implementing them. This is a good thing.

Example list:

verilog/negator.v, verilog/negator.cpp: the simplest non-identity combinatorial circuit!
verilog/counter.v, verilog/counter.cpp: sequential hello world. Synchronous active high reset with active high enable signal. Adapted from: www.asic-world.com/verilog/first1.html
verilog/subleq.v, verilog/subleq.cpp: subleq one instruction set computer with separated instruction and data RAMs

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