Verilog simulator that transpiles to C++.
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.
Some simulation examples under verilog.
First install Verilator. On Ubuntu:
sudo apt install verilator
Tested on Verilator 4.038, Ubuntu 22.04.
Run all examples, which have assertions in them:
cd verilator
make run
File structure is for example:
Example list:
The example under verilog/interactive showcases how to create a simple interactive visual Verilog example using Verilator and SDL.
https://raw.githubusercontent.com/cirosantilli/media/master/verilog-interactive.gif
You could e.g. expand such an example to create a simple (or complex) video game for example if you were insane enough. But please don't waste your time doing that, Ciro Santilli begs you.
Usage: install dependencies:
sudo apt install libsdl2-dev verilator
then run as either:
make run RUN=and2
make run RUN=move
Tested on Verilator 4.038, Ubuntu 22.04.
In those examples, the more interesting application specific logic is delegated to Verilog (e.g.: move game character on map), while boring timing and display matters can be handled by SDL and C++.