 Input capacitance

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.