Input capacitance ($C_{\mathrm{in}}$)

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.

Input capacitance inferred from measured admittance is a parameter estimate from the quadrature component of a specified electrical port's response. In the parallel model of input capacitance, write its electrical admittance as $Y=G+i\omega C$ with the $e^{i\omega t}$ convention. A small sinusoidal excitation and simultaneous input-current measurement giveBoth amplitude ratio and relative wave phase matter. The differential versus common-mode terminals and operating point conditions must be specified, as in the manufacturer's input-path diagrams.^[ref]

For an original error calculation, suppose the amplitude ratio is exact but the measured current-to-voltage wave phase has offset $\delta$. Then $Y_{\mathrm{meas}}=Y{e}^{i\delta }$ andThe phase calibration error in an admittance-based capacitance estimate can therefore mix a conductance term into the small capacitive estimate. For small $\delta$, the leading error is $(G/\omega )\delta$, not a fixed percentage of $C$.

Choose $G=10\mu \mathrm{S}$, $C=20\mathrm{pF}$, and $f=10\mathrm{kHz}$. The true susceptance is only $\omega C\approx 1.257\mu \mathrm{S}$. A one-degree wave phase offset yields $\hat{C}\approx 22.775\mathrm{pF}$, an error of about $13.9\%$, despite perfect amplitude readings. These are chosen port-model values, not measured device specifications.

A useful measurement repeats the estimate over frequency and excitation amplitude. A nearly constant fitted $C$ and a residual consistent with $G+i\omega C$ support the assumed model; they do not prove that all parasitic effects were removed. A known fixture admittance adds to a parallel port and must be subtracted or retained in the model. At very small susceptance, uncertainty in the relative wave phase can dominate, so a high DC input impedance alone is not evidence for a precise capacitance measurement.

Phase calibration error in an admittance-based capacitance estimate can rotate a large in-phase conductance into a small capacitive quadrature. In the parallel port model $Y=G+i\omega C$ with $G\ge 0$, $C>0$, and the $e^{i\omega t}$ convention, a relative wave phase error $\delta$ gives $Y_{\mathrm{meas}}=Y{e}^{i\delta }$. The exact estimate in input capacitance inferred from measured admittance therefore has relative errorThe ratio $G/(\omega C)$, not the DC resistance alone, determines sensitivity to a small wave phase rotation. The manufacturer's separate differential/common-mode port models motivate specifying the terminals and operating point before fitting an input capacitance.^[ref]

If $|\delta |\le ϵ\le \pi /2$, the worst absolute relative error is bounded byThe negative endpoint $\delta =-ϵ$ attains this bound. For target relative error $r>1-\cos ϵ$, a sufficient frequency condition isThis condition assumes the same $G+i\omega C$ model and the same phase-error bound remain valid over that frequency range.

For an original planning example, take $G=1\mu \mathrm{S}$, $C=50\mathrm{pF}$ and $ϵ=0.5^{\circ }$. The bound is about $2.782\%$ at $1\mathrm{kHz}$ and $0.282\%$ at $10\mathrm{kHz}$. A one-percent target requires approximately $f\ge 2.788\mathrm{kHz}$ in this model. Increasing frequency suppresses the conductance-mixing term, but leaves the $1-\cos ϵ$ term and can expose other unmodelled parasitic effects.

A measurement uses the same voltage/current wave phase reference for the ratio $I/V$, checks that reference with a known port, and retains fixture admittance in the model or subtracts a validated value. Amplitude measurement calibration alone cannot establish this wave phase bound. The numbers above are chosen calculations, not device specifications or a claim that a high-frequency measurement is automatically more accurate.