 Solution

For a CMOS inverter, connect one PMOS transistor from the positive supply $V_{DD}$ to the output and one NMOS transistor from the output to ground; drive both gates with the input $x$. When $x=0$, the PMOS transistor conducts and the NMOS transistor is off; when $x=1$, the reverse holds. Thus the output is $\neg x$, using two transistors.

For a four-input NAND gate, use four NMOS transistors in series between the output and ground, with gates $a,b,c,d$. Use four PMOS transistors in parallel between $V_{DD}$ and the output, with the same gate signals. The pull-down network conducts exactly when all four inputs are one; the pull-up network conducts whenever at least one input is zero. HenceAs usual for static CMOS, tie the NMOS transistor bodies to ground and the PMOS transistor bodies to $V_{DD}$.