CMOS

An integrated circuit technology using complementary MOSFETs. CMOS names a circuit technology; active-pixel sensor names a detector architecture.

A static CMOS implementation of a NAND gate has a pull-down network of NMOS transistors in series and a pull-up network of PMOS transistors in parallel. With $k$ inputs it uses $k$ devices of each kind. All inputs high connect the output to ground; any low input breaks the pull-down path and connects the output to the positive supply through its corresponding p-channel device.

For an NMOS transistor network described by a series-parallel expression in conducting inputs, replace series by parallel, parallel by series, and each device by a PMOS transistor driven by the same input. De Morgan's laws show recursively that the resulting pull-up network conducts exactly when the original pull-down network does not. This proves complementary rail connections for stable binary inputs in the ideal static model. Factoring a Boolean function before constructing its dual can remove duplicated devices: $ab\vee bc=b(a\vee c)$ needs three lower and three upper devices, instead of four of each. Physical switching transients, device sizing and delays are additional engineering questions.

A pull-down network connects a logic output to the low supply rail when its conducting condition holds. In static complementary CMOS, it is built from NMOS transistors; its conducting condition is the negation of the desired output Boolean function.

A pull-up network connects a logic output to the high supply rail when its conducting condition holds. In static complementary CMOS, it is built from PMOS transistors and paired with a complementary pull-down network.

A complementary p-channel/n-channel transistor pair with joined gates as input and joined drains as output. The p-channel device pulls toward the positive supply and the n-channel device toward ground, producing logic inversion with ideally zero settled-state through-current.