 Superscalar execution

Superscalar execution allows one CPU core to issue multiple machine instructions in a clock cycle to suitable execution resources. It exploits independent work within an instruction stream. This differs from instruction pipelining, which overlaps stages of different machine instructions and can still have an issue width of one.

For example, a=b+c and d=e+f may execute together if both operands and execution units are available. In a=b+c; d=a+f, the second addition depends on the first result and cannot use it before it is ready. Issue width is consequently a capacity, not a guaranteed completed-instruction count every cycle. Arm describes the Cortex-A8 as a dual-issue design that retains instruction order, illustrating that superscalar execution does not require out-of-order execution.^[ref]