Instruction pipelining divides execution into stages with stored intermediate state, allowing different instructions to occupy different stages simultaneously. The processor clock period is constrained by stage timing; moving a barrel shifter and arithmetic logic unit into the same stage can lengthen that stage's combinational critical path.
An execution-timing conflict arising from the ordering of accesses to a value. A read-after-write hazard occurs when a consumer would read before its required producer's value becomes available.
A younger instruction needs a value produced by an older instruction before the ordinary writeback/read path would deliver it. Register forwarding or a pipeline stall can enforce the true dependence.
Sending an already produced result directly to a consumer without waiting for its write to the register file. The bypass must choose the youngest older writer whose value is ready.
An interval in which some stage cannot advance its instruction. A data hazard, occupied resource or unresolved cache miss can cause a pipeline stall.
Storage between stages of an instruction pipelining implementation, holding intermediate operands, results and control information across a clock boundary.
An instruction pipelining organization in which instructions advance through execution in program order. Different instructions can occupy different stages simultaneously, and register forwarding can remove some data hazards.
