In classic delayed-control-transfer MIPS, the instruction immediately after a branch or jump executes before control transfers. A harmless sll $zero,$zero,0 can fill that slot. A jump-and-link records the address after this slot as its return address.[ref]

Ancestors (4)

  1. MIPS architecture
  2. Instruction set architecture
  3. Computer science
  4. Home

Incoming links (3)

View article source

Discussion (0)

New discussion

There are no discussions about this article yet.

Articles by others on the same topic (0)

There are currently no matching articles.
See all articles in the same topic Create my own version