Instruction set architecture

The programmer-visible machine instruction repertoire and its semantics, including accessible processor registers and permitted operand forms. Different processors can implement the same instruction set architecture using different internal designs.

An addressing mode specifies how an instruction obtains an operand or forms an effective memory address. Examples include immediate operands, processor register operands, base-plus-displacement memory access and scaled processor register indexing.

An immediate operand is a value encoded in an instruction rather than fetched from a processor register or a separate memory location. Its width and interpretation limit the available values; scaling an encoded field can trade address granularity for displacement range.

Scaled index addressing forms a memory address $B+sI$ from a base $B$ and index $I$. For element size $s=2^k$, a barrel shifter forms the displacement by a left bit shift before the arithmetic logic unit adds the base. This directly implements array indexing without a separate multiplication instruction.

SP-relative addressing adds an encoded displacement to the stack pointer. Scaling an immediate operand by a power of two reaches farther with the same field width but restricts the address grid. An eight-bit nonnegative field scaled by four reaches $0,4,\dots ,1020$, whereas scaling it by sixteen reaches $0,16,\dots ,4080$; it does not provide every intervening byte address.

A machine-encoded operation executed by a processor. An assembly language mnemonic can denote one machine instruction or an assembler expansion into several.

The arrangement of bits specifying an operation, its operands and any immediate constants. A fixed-width encoding has a finite budget shared between these fields.

An operation-selecting field of a machine instruction. A primary opcode can select a family whose individual operations are distinguished by secondary function fields.

A family of reduced instruction set computer architectures. The classic 32-bit integer encoding has five-bit processor register fields, while many branch and jump instructions execute a branch delay slot. These conventions differ from later revisions and must be stated when presenting assembly language.

In classic delayed-control-transfer MIPS, the instruction immediately after a branch or jump executes before control transfers. A harmless sll $zero,$zero,0 can fill that slot. A jump-and-link records the address after this slot as its return address.^[ref]

The classic 32-bit layout is $\mathrm{op}:6,\mathrm{rs}:5,\mathrm{rt}:5,\mathrm{immediate}:16$. The second register field is named $\mathrm{rt}$, including when it denotes a destination; there is no separate $\mathrm{rd}$ field.

The classic 32-bit layout is $\mathrm{op}:6,\mathrm{rs}:5,\mathrm{rt}:5,\mathrm{rd}:5,\mathrm{shamt}:5,\mathrm{funct}:6$. Not every operation uses every field.

A family of processor architectures with several execution states and instruction encodings. The 32-bit instruction sets include the compact Thumb instruction set; the 32-bit AAPCS32 calling convention specifies interoperation at subroutine boundaries.

A compact instruction encoding for the ARM architecture family, with sixteen-bit encodings and, in later versions, additional thirty-two-bit encodings. Operand restrictions depend on the selected architecture. The original sixteen-bit signed halfword load uses a register offset, whereas an ordinary halfword load also offers an immediate offset.^[ref]