Carry flag ($C$)

A processor status bit recording arithmetic carry. For unsigned addition of $n$-bit inputs, $X+Y=Z+2^{n}C$, where $Z$ is the stored result. In the ARM architecture family, subtraction instead uses $X-Y=Z-2^n(1-C)$, so a set arithmetic carry means no borrow. This convention must be checked for the target instruction set; it is not a signed-overflow test.

With the ARM architecture family's no-borrow convention, subtract with carry forms $X-Y-(1-C_{\mathrm{in}})$. The same adder used for addition can form $X+(2^n-1-Y)+C_{\mathrm{in}}$. If its output is $Z+2^n{C}_{\mathrm{out}}$, rearranging proves $X-Y-(1-C_{\mathrm{in}})=Z-2^n(1-C_{\mathrm{out}})$. Thus complementing the second operand implements both the result and the correctly chained borrow information.^[ref]

For $n$-bit operands, an add with carry operation forms $X+Y+C_{\mathrm{in}}$, retains its residue modulo $2^n$, and outputs its arithmetic carry. Adding low limbs first and feeding each arithmetic carry into the next limb implements multiword unsigned addition. With $M=2^n$, the identities $X_0+Y_0=Z_0+Mc$ and $X_1+Y_1+c=Z_1+Md$ combine into $(M{X}_1+X_0)+(M{Y}_1+Y_0)=M{Z}_1+Z_0+M^{2}d$.^[ref]