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Given a finite acyclic Boolean circuit and its input assignment, determine the output bit. Topological gate evaluation places the problem in P; it is a standard P-complete problem under logspace many-one reductions. Boolean circuit evaluation is different from Circuit satisfiability problem, which asks whether some assignment succeeds.

The problem belongs to NP: an assignment in ${\mathbb{F}}_2^n$ is a polynomial-length certificate in computational complexity, and substitution verifies every equation in polynomial time.

For NP-hardness, reduce the Circuit satisfiability problem. Introduce one variable in ${\mathbb{F}}_2$ for every wire of a Boolean circuit. A logical negation gate $w=\neg u$ is enforced by $w=1-u$, and a logical conjunction gate $w=u\wedge v$ is enforced by $w=uv$. For a logical disjunction gate use the suggested quadratic equationwhich is equivalent to $w=u\vee v$ for bits $u,v,w$. Add the linear equation $w_{\mathrm{out}}=1$ for the designated output wire.

The construction introduces one variable and one equation per wire or gate, so it is a polynomial-time many-one reduction. A satisfying circuit input extends uniquely through its gates to a solution of the equations, and any solution gives a consistent accepting circuit computation. Since circuit satisfiability is NP-complete, quadratic-equation satisfiability over F2 is therefore

Quadratic-equation satisfiability over F2 asks whether finitely many polynomials of polynomial degree at most two over the finite field ${\mathbb{F}}_2$ have a common zero. Each unknown therefore takes one of the two truth values zero and one, with addition and multiplication performed modulo two.

A Boolean circuit can be encoded by introducing a Boolean variable for every logic gate output. An AND gate $z=x\wedge y$ becomes $z+xy=0$, while a NOT gate $z=\neg x$ becomes $z+x+1=0$. Forcing the final output to one adds $z_{\mathrm{out}}+1=0$. All these constraints have degree at most two, and an assignment to the logic gate variables solves them exactly when it is a consistent accepting Boolean circuit evaluation.

The construction has polynomial size and reduces the Circuit satisfiability problem to this task. Guessing values and checking the displayed polynomials proves membership in NP, so the problem is NP-complete. This explains why allowing quadratic terms changes the computational picture from a system of linear equations solved by Gaussian elimination.