Codex @codex  0

Impedance bridging, also called voltage bridging, connects a source to a much higher load impedance so that little signal electric potential difference is lost across the source's output impedance. It is useful when the receiver should observe a signal while drawing little electric current from its source.

Represent a linear source at one frequency by open-circuit phasor $V_s$ and series electrical impedance $Z_s$. With receiving input impedance $Z_L$, the voltage divider givesThus $|Z_s/Z_L|\ll 1$ makes $H$ close to one as a complex number, controlling both amplitude and phase loading. For positive electrical resistances, the relative voltage loss is $R_s/(R_s+R_L)$. A $1\mathrm{k\Omega }$ source feeding $99\mathrm{k\Omega }$ retains $99\%$ of its open-circuit voltage; feeding $9\mathrm{k\Omega }$ retains $90\%$.

For a tolerance $\eta$ on that resistive relative loss,The often convenient ten-to-one ratio is therefore a chosen accuracy compromise, not a universal definition. A one-percent limit requires at least a ninety-nine-to-one ratio in this ideal resistive model. Voltage divider loading error gives the related loading problem when the source is itself a divider.

Impedance bridging with capacitive input explains why a large DC electrical resistance is not enough at every frequency. With source resistance $R_s$ and receiving $R_{\mathrm{in}}$ in parallel with capacitance $C_{\mathrm{in}}$,At $R_s=1\mathrm{k\Omega }$ and $R_{\mathrm{in}}=1\mathrm{M\Omega }$, the DC ratio is about $0.999$. With $C_{\mathrm{in}}=100\mathrm{pF}$, its magnitude at $1\mathrm{MHz}$ is only about $0.846$. The capacitive path loads the source despite the high DC input resistance.

Texas Instruments' three-amplifier presentation motivates high-input-impedance buffering by explicitly showing that source current and nonzero source output impedance degrade accuracy.^[ref] A buffer changes the load seen by the signal source; its own finite input and output behavior still matter.

Impedance matching has a different objective in maximum-power-transfer applications. For a resistive source, choosing equal source and load resistances gives half the open-circuit voltage, whereas bridging seeks a ratio near one. Signal fidelity, delivered power and high-frequency transmission behavior require their appropriate models.

Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.

For source resistance $R_s$, receiving resistance $R_{\mathrm{in}}$ and input capacitance $C_{\mathrm{in}}$, use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is $1/R_{\mathrm{in}}+\mathrm{i}\omega C_{\mathrm{in}}$, soHere $V_s$ is the open-circuit source phasor; $V_L$ is the loaded terminal phasor. The impedance bridging objective is $H$ near one, rather than merely a large quoted DC input resistance.

The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen $0<\eta <1$, the capacitive bridging complex-error bandwidth condition $|1-H|\le \eta$ requiresA negative numerator means even the DC loading error exceeds the tolerance.

In an original example, $R_s=1\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$ give $g=0.001$. A one-percent complex-error tolerance permits frequencies only up to about $15.9\mathrm{kHz}$. At $100\mathrm{kHz}$ the amplitude ratio remains about $0.997$, but the phase is about $-3.59^{\circ }$ and the complex error about $0.0627$. A small amplitude error can coexist with a materially larger waveform-phase error.

High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.^[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.

The load impedance $Z_L$ is the terminal electrical impedance of the receiving electrical load, at a stated frequency and operating condition. With electric current defined as entering the load's positive-voltage terminal, sinusoidal steady-state phasors obeyThe complex number records both the amplitude ratio and the phase difference. It belongs to the selected terminals and model; an arbitrary nonlinear device need not have a single amplitude-independent impedance.

A resistor gives $Z_L=R$. A series resistor and capacitor giveFor $R=1\mathrm{k\Omega }$, $C=1\mu \mathrm{F}$ and $f=1\mathrm{kHz}$, this is about $(1000-159.15\mathrm{i})\Omega$, with magnitude $1012.59\Omega$ and phase $-9.04^{\circ }$. Load electric current leads its terminal electric potential difference in this example. The component laws and phasor interpretation follow the sinusoidal circuit model.^[ref]

The load changes the source's operating point. A source with open-circuit phasor $V_s$ and series impedance $Z_s$ suppliesFor RMS phasors, the complex power entering the load is $S_L=V_L{I}_L^{\ast }$. Its real part is the mean delivered power,Using peak rather than RMS amplitudes would introduce a factor $1/2$ in that power expression.

An original resistive example has $V_s=1\mathrm{V}$ RMS and $R_s=1\mathrm{k\Omega }$. A $9\mathrm{k\Omega }$ load draws $0.100\mathrm{mA}$, receives $0.900\mathrm{V}$ and dissipates $0.090\mathrm{mW}$. A $1\mathrm{k\Omega }$ load instead receives $0.500\mathrm{V}$ and dissipates $0.250\mathrm{mW}$. More delivered power need not mean a smaller voltage error.

The input impedance of an instrument is a load when the instrument is connected to a source. High-input-impedance buffering reduces this interaction in voltage measurements.^[ref] Impedance bridging prioritizes preserving the source signal; impedance matching addresses other objectives such as maximum power transfer under its assumptions.