Integrator reset 2026-11-05
An integrator reset establishes the charge on an integrating amplifier's feedback capacitor before the next measurement. Without it, the next output includes the previous initial condition, and repeated input pulses or input offset voltage can eventually cause amplifier clipping. Resetting makes consecutive measurement intervals comparable; it does not reconstruct a pulse already lost to amplifier clipping.
Consider an inverting integrating amplifier with the input held at zero during reset. Place an analog switch across its feedback capacitor . In the approximation of a stable ideal operational amplifier maintaining a virtual ground, a closed switch with constant on-state electrical resistance gives the RC circuit relation
This exponential decay gives an integrator reset settling time for residual magnitude at most :
For stipulated values , and , the reset time constant is . Reaching a residual of requires about in this model. Actual amplifier drive, stability and recovery from overload can change the response. A switch's control delay also differs from the full circuit's settling time.[ref]
Opening the reset switch can itself disturb the initial condition. Analog switch charge injection transfers a small charge to the connected capacitor, producing a reset charge-injection pedestal of magnitude
For a stipulated deposited on , this step is . Its sign depends on the circuit and charge direction. A longer reset suppresses the preceding exponential residual but need not suppress the new step created when the switch opens. Analog Devices illustrates this capacitive coupling mechanism and the resulting output step separately from retained-charge settling.[ref]
A practical experiment repeats zero-input measurements with several reset durations and reads the output at the same delay after switch opening. A decreasing residual indicates incomplete discharge; a persistent offset can instead include reset charge-injection pedestal, input offset voltage and subsequent drift. Repeated readings help separate the reproducible offset from noise. The ACF2101 provides a concrete historical implementation: separate hold and reset controls disconnect the input and discharge the integration capacitor, and its datasheet shows the sequence of hold, integration and reset states.[ref]
The reset interval also creates integrator reset dead time: charge arriving while the circuit is being reset may not contribute to the next measured integral. Pulse timing relative to the reset therefore matters. A perfectly repeatable baseline alone does not establish that every input pulse was captured.
The integrator reset settling time is the time required to reach a stated error band under the reset/readout sequence. It is not merely the switch's control propagation delay. The primary switch tutorial distinguishes switching time from complete-circuit settling.[ref]
The integrator reset article derives an ideal residual , with . A focused extension includes an opening pedestal whose magnitude is at most . A conservative final-error bound is
To guarantee from this bound, require and
when the logarithm is positive. This reset error budget with a persistent pedestal assigns separate parts of the tolerance to the residual and the opening event.
For stipulated , , and , the required duration is about . A tolerance of cannot be guaranteed by waiting longer under the same pedestal bound. Accidental cancellation of opposite-sign errors is not a worst-case guarantee.
Measure the output against a stated band at a reproducible delay after opening. Ringing, amplifier drive limits and prior overload can invalidate a single-exponential model; the device datasheet treats output-overload recovery separately.[ref] The resulting acquisition exclusion is part of integrator reset dead time.