Past exam of the year 1 of the computer science course of the University of Oxford / 2013 / Digital systems, linear algebra, introduction to formal proof / 2 / c

Choose ToAlu=0 for the $va{l}_t$ input and ToAlu=1 for the expanded immediate operand. Choose ToReg=0 for the arithmetic logic unit result and ToReg=1 for memory read data. The diagram does not label the multiplexer polarities, so these are explicit conventions.

Let $F_{+}$ and $F_{\vee }$ denote the six-bit arithmetic logic unit operation codes for addition and bitwise OR. Their numerical codes are not specified by the paper. The opcode needs to distinguish register, immediate, load and store modes; add and or can share register mode, and addi and ori can share immediate mode, since $15:10$ selects the operation directly. For example, choose $o_R=000000$, $o_I=000001$, $o_L=000010$ and $o_S=000011$. With $X$ denoting a field whose bits do not matter, the formats are:

The required opcode control table is:

Here MemRd is irrelevant whenever read data is unused, under the ordinary side-effect-free memory interpretation of the diagram. It is sensible to choose zero for those $X$ entries to save activity; memory-mapped devices with read side effects would require that choice. For store, ToReg is irrelevant because $r_d=0$; ToAlu is essential because its output supplies both the second arithmetic logic unit operand and memory write data. For load, the memory address is $va{l}_s$ independently of ToAlu and of $15:10$.

The resulting effects, with 32-bit addition, arewhere $E(x)=(x\mathrm{mod}256)2^{8\lfloor x/256\rfloor }$ for the ten-bit field $x$.