Past exam of the year 1 of the computer science course of the University of Oxford / 2017 / Digital systems, linear algebra, introduction to formal proof / 3 / b / iii / Solution

For add, select rd and the arithmetic logic unit result. For sw, select destination zero while retaining the memory-store controls and source-register reads. For jal, select register 31 and the return-address data. These are the same actual register writes as before, with sw using destination zero in place of disabling RegWrite.

The link value is determined by the particular MIPS architecture datapath convention: $\mathrm{PC}+4$ for the usual teaching datapath without a delay slot, or $\mathrm{PC}+8$ for classic delayed-branch MIPS. This write-enable change does not alter whichever link convention the original machine implements.