Past exam of the year 1 of the computer science course of the University of Oxford / 2017 / Digital systems, linear algebra, introduction to formal proof / 3

Use $k$ clocked processor registers, each storing an $n$-bit word, two independent combinational read ports and one synchronous write port. Each address requires $a=\lceil {\log }_{2}k\rceil$ bits. The read addresses select two $k$-to-one multiplexers, each $n$ bits wide. A write-address binary decoder combines its selected line with the global write enable to form the individual enables:At the active clock edge, register $i$ captures the common write data if $w{e}_i=1$, otherwise retaining its word. Reads return the currently stored words selected by their respective addresses. For non-power-of-two $k$, unused address codes need a specified harmless implementation. A simultaneous read and write of one address follows the chosen edge/read timing; an additional forwarding circuit would be needed if a different bypass convention were required.

Keep storage only for registers 1 through 31, return a hardwired all-zero word on either read port when its address is zero, and setThere is no enable for register zero and no global RegWrite input to this register file. The right-hand diagram above shows this change. Every clock edge may select a write address; choosing zero suppresses all physical register enables. Consequently the MIPS zero register acts as a write-suppression destination.

Move the no-write decision into the destination-address path. If the original destination selection produced $d$ and the original write-enable decision was $W$, drive the new register file withA five-bit two-input multiplexer after the existing destination selector implements this, or the decoder can directly select among zero, the instruction's destination fields and register 31. Its control still distinguishes writing and non-writing instructions: removing the register-file enable pin does not remove that logical decision.

Read-address selection and the result-data path can remain unchanged. Instructions that formerly disabled RegWrite now select destination zero; their write data is irrelevant. Instructions writing an actual destination preserve the same address and data. Since writes to the MIPS zero register were already discarded, the architectural behaviour is unchanged for that case as well.

For add, select rd and the arithmetic logic unit result. For sw, select destination zero while retaining the memory-store controls and source-register reads. For jal, select register 31 and the return-address data. These are the same actual register writes as before, with sw using destination zero in place of disabling RegWrite.

The link value is determined by the particular MIPS architecture datapath convention: $\mathrm{PC}+4$ for the usual teaching datapath without a delay slot, or $\mathrm{PC}+8$ for classic delayed-branch MIPS. This write-enable change does not alter whichever link convention the original machine implements.