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Clock frequency is the number of cycles of a clock signal per unit time. If its period is $T_c$, its frequency is $f=1/T_c$. A $3\times 10^9$ hertz clock has a nominal period of about $0.333\times 10^{-9}$ seconds. The clock coordinates timed operations; it does not specify how many complete program instructions are performed in each cycle.

For a fixed-frequency processor, execution time can be written as instruction count times average cycles per instruction divided by frequency. Raising frequency can improve that component of runtime, but it may also require a different pipeline organization or increase power and thermal constraints. Memory waits and dependencies can leave some cycles without completed instructions, while superscalar execution can complete several instructions in one cycle. Performance comparisons must therefore include the workload and microarchitecture, not only the clock rating.

Superscalar execution allows one CPU core to issue multiple machine instructions in a clock cycle to suitable execution resources. It exploits independent work within an instruction stream. This differs from instruction pipelining, which overlaps stages of different machine instructions and can still have an issue width of one.

For example, a=b+c and d=e+f may execute together if both operands and execution units are available. In a=b+c; d=a+f, the second addition depends on the first result and cannot use it before it is ready. Issue width is consequently a capacity, not a guaranteed completed-instruction count every cycle. Arm describes the Cortex-A8 as a dual-issue design that retains instruction order, illustrating that superscalar execution does not require out-of-order execution.^[ref]