A compact instruction encoding for the ARM architecture family, with sixteen-bit encodings and, in later versions, additional thirty-two-bit encodings. Operand restrictions depend on the selected architecture. The original sixteen-bit signed halfword load uses a register offset, whereas an ordinary halfword load also offers an immediate offset.[ref]
Thumb 16-bit instruction set quick reference by Arm. Load entries: halfword immediate/register and signed halfword register
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