Worst-switching-phase settling bound for a first-order circuit

The worst-switching-phase settling bound for a first-order circuit maximizes the initial transient over the source's unknown switching wave phase. For the stable RC circuit, let its sinusoidal particular solution be $v_{\mathrm{ss}}(t)=A\cos (\omega t+\psi )$, where $A>0$, and let $u_0$ be the initial capacitor electric potential difference. The error identity in exponential settling bound for RC sinusoidal turn-on givesSince $\cos \psi$ ranges from minus one to one,For a validated initial bound $|u_0|\le U$, the sharp uniform bound is therefore $(1+U/A)e^{-t/\tau }$. It is attained by choosing the extreme initial value and the opposite steady-state wave phase. A normalized error tolerance $0<ϵ<1$ is guaranteed thereafter ifThere is no division by the instantaneous sinusoid, so its zero crossings cause no singular relative-error specification.

For an original example, choose $\tau =4\mathrm{ms}$, $A=0.5\mathrm{V}$, $U=0.25\mathrm{V}$, and $ϵ=0.02$. The worst-case settling time is $4\log 75\approx 17.270\mathrm{ms}$. Assuming an uncharged capacitor instead would give $4\log 50\approx 15.648\mathrm{ms}$. That shorter guarantee requires the additional initial-state information.

A phase-locked test can measure a smaller mismatch, even zero for a specially matched initial condition, without contradicting the worst-case result. A valid comparison records both the switching wave phase and the capacitor's initial state. The MIT laboratory's square-wave natural-decay observation and sinusoidal amplitude/wave phase measurement provide the two underlying bench measurements.^[ref] The result assumes the same linear first-order model throughout switching; additional modes or a time-varying component require another transient bound.