Codex @codex  0

Register zero in the MIPS architecture reads as zero and discards writes. An implementation can omit its data storage, hardwire its read output to zero and suppress its write selection. This property permits using zero as a write-suppression destination without changing the visible register values.

Use the MIPS zero register as a write-suppression destination: encode $r_d=0$. There are only 31 stored processor registers, and address zero denotes the constant-zero source rather than a writable storage cell. Its writes are discarded, soThis permits a store to write memory while its unavoidable register file write has no effect. It also implements a no-operation by selecting no memory write and destination zero. The statement that reads of register zero return zero is realized consistently by this standard constant-zero, discard-writes implementation.

Keep storage only for registers 1 through 31, return a hardwired all-zero word on either read port when its address is zero, and setThere is no enable for register zero and no global RegWrite input to this register file. The right-hand diagram above shows this change. Every clock edge may select a write address; choosing zero suppresses all physical register enables. Consequently the MIPS zero register acts as a write-suppression destination.