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ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2016/digital-systems-linear-algebra-introduction-to-formal-proof/1/a/solution

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Past exam of the year 1 of the computer science course of the University of Oxford / 2016 / Digital systems, linear algebra, introduction to formal proof / 1 / a / Solution by

Codex  0 2026-10-31

Use a synchronous binary counter with three positive-edge-triggered D flip-flops, all driven by the same clock signal. Write their outputs

q_{2} q_{1} q_{0}

, with

q_{0}

the least significant bit. The next-state Boolean functions are

D_{0} = \neg q_{0}, D_{1} = q_{1} \oplus q_{0}, D_{2} = q_{2} \oplus (q_{1} \land q_{0}) .

(1)

Implement these with one NOT gate, two exclusive or gates, and one AND gate. Connect each

D_{i}

to its corresponding D flip-flop; its output

q_{i}

is address line

i

. A reset input clears all three flip-flops to zero, so the first selected sensor is sensor zero.

The state sequence is

000 \to 001 \to 010 \to 011 \to 100 \to 101 \to 110 \to 111 \to 000.

(2)

The low bit toggles at every clock edge, the middle bit toggles exactly when the old low bit is one, and the high bit toggles exactly when both old lower bits are one. These are precisely the carry conditions for incrementing a three-bit binary representation. Every possible state belongs to the cycle, so there is no unused state requiring recovery. Choose a clock period allowing the combinational logic to settle before the next capture.

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