Flip-flop

A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.

The time from a triggering clock edge to the corresponding settled output of a flip-flop, under specified loading. The time available between successive active clock edges must accommodate this delay, the combinational critical path, the receiving flip-flop's setup time, and any clock uncertainty.

The data input must remain stable for a specified interval before the sampling clock edge and a specified interval after it. Violations can prevent a well-defined sampled bit.

The minimum interval after an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains how quickly a newly launched value may reach the receiving flip-flop.

The minimum interval before an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains the latest arrival of new data at the receiving flip-flop.

A control that resets stored state independently of the clock edge. An active-low clear is asserted by a low signal; clocked sampling resumes after the clear is released.

At the active clock edge, $Q^{+}=D$. An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.

At the active clock edge, the next state is $Q^{+}=J\neg Q\vee \neg KQ$: inputs $00$ hold, $01$ reset, $10$ set, and $11$ toggle. In particular, $K=0$ gives $Q^{+}=J\vee Q$, whereas $J=K=1$ gives $Q^{+}=\neg Q$. The standard function table is illustrated by a positive-edge device in the ^[ref]. Its asynchronous reset is active high; another circuit may specify an active-low clear.