Addressing mode

An addressing mode specifies how an instruction obtains an operand or forms an effective memory address. Examples include immediate operands, processor register operands, base-plus-displacement memory access and scaled processor register indexing.

An immediate operand is a value encoded in an instruction rather than fetched from a processor register or a separate memory location. Its width and interpretation limit the available values; scaling an encoded field can trade address granularity for displacement range.

An instruction encoding that stores an eight-bit byte and a two-bit byte-position selector, expanding them to a 32-bit machine word as $b{2}^{8j}$ for $0\le j\le 3$. Four such values can construct any 32-bit constant using bitwise OR or addition modulo $2^{32}$.

Widen an $m$-bit binary representation to $w>m$ bits by retaining the original low positions and filling every new high position with zero. This preserves the unsigned interpretation. A MIPS instruction such as ori uses zero extension of its immediate operand, whereas addi uses sign extension.

Scaled index addressing forms a memory address $B+sI$ from a base $B$ and index $I$. For element size $s=2^k$, a barrel shifter forms the displacement by a left bit shift before the arithmetic logic unit adds the base. This directly implements array indexing without a separate multiplication instruction.

SP-relative addressing adds an encoded displacement to the stack pointer. Scaling an immediate operand by a power of two reaches farther with the same field width but restricts the address grid. An eight-bit nonnegative field scaled by four reaches $0,4,\dots ,1020$, whereas scaling it by sixteen reaches $0,16,\dots ,4080$; it does not provide every intervening byte address.