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An analog switch uses a control signal to connect or disconnect an analog signal path. The control chooses the conducting state; the transmitted electric potential difference is not restricted to a binary logic value. Real devices have finite analog switch on-resistance, leakage and parasitic capacitance. The primary tutorial describes a bilateral CMOS switch formed from complementary transistors.^[ref]

For an original loading example, connect an ideal $1\mathrm{V}$ source through a stipulated $100\Omega$ on-resistance to a $10\mathrm{k\Omega }$ load. The output isThe closed switch therefore changes the amplitude even before any switching transient is considered. This is a chosen resistor model, not a specification for a particular part. Variation of on-resistance with signal level can additionally produce distortion.

An open switch is also not an ideal infinite impedance. For example, a stipulated $10\mathrm{nA}$ analog switch leakage current into $100\mathrm{pF}$ changes the node potential at $I/C=100V/s$, or $0.10\mathrm{V}$ in a millisecond if that model remains valid. A high-impedance measurement can be sensitive to this small current.

On a bench, compare the transmitted level and the open-state drift with the same source, load and oscilloscope conditions. Analog switch charge injection concerns the control transition itself, while settling time concerns how long the complete circuit needs to approach its final value. Those effects are separate from the static conducting-state error.

Analog switch leakage current is unwanted electric current at an analog switch's signal terminals under stated terminal potentials, switch state and temperature. It can produce a steady offset in a resistive load or accumulate electric charge on an isolated capacitor. The manufacturer's equivalent circuits distinguish on-state and off-state leakage paths; their effects depend on the external circuit.^[ref]

For an original chosen model, let a constant $20\mathrm{pA}$ enter a node with a $50\mathrm{M\Omega }$ resistor to a reference. The steady electric potential difference error is $IR=1.0\mathrm{mV}$. Replacing that load by an initially isolated $200\mathrm{pF}$ capacitor instead givesA $100\mu \mathrm{V}$ drift allowance is exhausted in $1.0\mathrm{ms}$. This leakage-limited hold time assumes constant leakage and capacitance; it ceases to apply if the changing node potential substantially changes the leakage. With both the resistor and capacitor present, $Cdv/dt=I_{\mathrm{leak}}-v/R$ approaches the steady error exponentially.

To measure the effect, hold the switch control fixed, disconnect the intended signal current and record the stored-node slope with known total capacitance. Repeat for relevant terminal potentials and temperatures. Readout input current and board leakage must be included in the measurement model. A one-time step at a control transition instead suggests analog switch charge injection; a sustained slope after that step is a different error mechanism.

An integrator reset establishes the charge on an integrating amplifier's feedback capacitor before the next measurement. Without it, the next output includes the previous initial condition, and repeated input pulses or input offset voltage can eventually cause amplifier clipping. Resetting makes consecutive measurement intervals comparable; it does not reconstruct a pulse already lost to amplifier clipping.

Consider an inverting integrating amplifier with the input held at zero during reset. Place an analog switch across its feedback capacitor $C$. In the approximation of a stable ideal operational amplifier maintaining a virtual ground, a closed switch with constant on-state electrical resistance $R_{\mathrm{on}}$ gives the RC circuit relationThis exponential decay gives an integrator reset settling time for residual magnitude at most $\epsilon$:For stipulated values $C=10\mathrm{nF}$, $R_{\mathrm{on}}=10\mathrm{k\Omega }$ and $|V_{\mathrm{old}}|=0.50\mathrm{V}$, the reset time constant is $100\mu \mathrm{s}$. Reaching a residual of $1\mathrm{mV}$ requires about $621\mu \mathrm{s}$ in this model. Actual amplifier drive, stability and recovery from overload can change the response. A switch's control delay also differs from the full circuit's settling time.^[ref]

Opening the reset switch can itself disturb the initial condition. Analog switch charge injection transfers a small charge to the connected capacitor, producing a reset charge-injection pedestal of magnitudeFor a stipulated $10\mathrm{pC}$ deposited on $10\mathrm{nF}$, this step is $1\mathrm{mV}$. Its sign depends on the circuit and charge direction. A longer reset suppresses the preceding exponential residual but need not suppress the new step created when the switch opens. Analog Devices illustrates this capacitive coupling mechanism and the resulting output step separately from retained-charge settling.^[ref]

A practical experiment repeats zero-input measurements with several reset durations and reads the output at the same delay after switch opening. A decreasing residual indicates incomplete discharge; a persistent offset can instead include reset charge-injection pedestal, input offset voltage and subsequent drift. Repeated readings help separate the reproducible offset from noise. The ACF2101 provides a concrete historical implementation: separate hold and reset controls disconnect the input and discharge the integration capacitor, and its datasheet shows the sequence of hold, integration and reset states.^[ref]

The reset interval also creates integrator reset dead time: charge arriving while the circuit is being reset may not contribute to the next measured integral. Pulse timing relative to the reset therefore matters. A perfectly repeatable baseline alone does not establish that every input pulse was captured.

The leakage-limited hold time is the duration for which a stored electric potential difference remains within a stated drift allowance when unwanted electric current changes the stored electric charge. For a constant net leakage $I_{\mathrm{leak}}$ into a fixed capacitance $C$,An allowed drift $\epsilon >0$ therefore gives $T_{\max }=C\epsilon /|I_{\mathrm{leak}}|$. This is a limit from a specified error mechanism, not the complete accuracy or usable duration of an instrument. The ACF2101 datasheet identifies amplifier bias, capacitor leakage and switch leakage as separate contributions to droop.^[ref]

For an original example, a4.7nanofarad capacitor,50picoamperes of net leakage and a0.20millivolt drift allowance giveIf the readout adds a further30picoamperes in the same direction, the correct total is80picoamperes and the duration falls to11.75milliseconds. The relevant electric current is the sum of all paths at the stored node, not necessarily the isolated analog switch leakage current specification.

For time-dependent leakage, the exact charge balance isA verified bound $|I_{\mathrm{net}}(t)|\le I_{\max }$ guarantees $|\Delta v(T)|\le I_{\max }T/C$. Oppositely signed contributions can cancel at one operating point without providing that bound elsewhere. Temperature, terminal potentials and board leakage must match the intended operating conditions.^[ref]

A bench check records the held node at several delays after the switching transient, using a known total capacitance and a readout whose input current is included in the model. The slope estimates net leakage. A step created at the transition is analog switch charge injection, not steady droop. If the initial step already uses part of a total error allowance, only the remaining allowance is available for calculating the leakage-limited hold time.